user-doc: add u-boot building and sunxi-fel

user-doc/user-doc.tex

@@ -66,6 +66,9 @@
 }
 \makeatother
 
+\makeatletter
+\global\let\tikz@ensure@dollar@catcode=\relax
+\makeatother
 
 \begin{document}
 
@@ -80,9 +83,48 @@
 
 \section{Introduction}
 
-\section{Flashing ROTS}
+\section{Building ROTS}
+
+\subsection{u-boot}
+
+At the moment of writing, the mainline version of u-boot does not have support for SPI NOR flash on Allwinner SoCs such as the Allwinner A10, A20 and the A64.
+A driver model compatible SPI driver for u-boot is has been worked on and the code can be found at \url{https://github.com/StephanvanSchaik/u-boot/tree/sunxi-spi}.
+This driver has been tested on the following boards:
+
+\begin{itemize}[noitemsep]
+\item H2+ Orange Pi Zero with Macronix MX25L1605D 16 Mbit
+\item A20 OLinuXino LIME 2 with Winbond W25Q128BV 128 Mbit
+\item A64 Pine64+ with Winbond W25Q128BV 128 Mbit
+\item A64 OLinuXino with Eon EN25Q64 64 Mbit
+\end{itemize}
+
+To compile u-boot with support for SPI NOR flash:
+
+\begin{minted}{text}
+git clone https://github.com/StephanvanSchaik/u-boot -b sunxi-spi
+make clean
+make A20-OLinuXino-Lime2_defconfig
+CROSS_COMPILE=armv7a-hardfloat-linux-gnueabi- make
+\end{minted}
+
+After u-boot-sunxi-with-spl.bin has been built, we can put it on an SD card as follows to test it:
+
+\begin{minted}{text}
+dd if=u-boot-sunxi-with-spl.bin of=/dev/sda bs=1024 seek=8
+\end{minted}
+
+While U-boot also supports booting from SPI NOR flash, it has been disabled by default:
+
+\begin{minted}{text}
+make menuconfig
+\end{minted}
 
-\subsection{}
+Enable the CONFIG\_SPL\_SPI\_SUNXI option.
+It is possible that the resulting binary will be too large.
+In that case, an option like CONFIG\_SPL\_MMC\_SUPPORT can be disabled to save some space.
+After the configuration options have been set up, rebuild the u-boot binary again.
+
+\section{Flashing ROTS}
 
 \subsection{Using an External Programmer}
 
@@ -224,4 +266,28 @@ To protect the range, we have to enable write protection as follows:
 Upon enabling write-protection, the \emph{Write-Protect} (WP) pin has to be pulled low for the write-protection to be effective.
 This prevents the user from disabling the write-protection feature, changing the write-protect range and from writing to the write-protected region.
 
+\subsection{Using sunxi-fel}
+
+Download and compile the \emph{sunxi-fel} tool as follows:
+
+\begin{minted}{text}
+git clone -b spiflash-a20-test https://github.com/ssvb/sunxi-tools.git
+make
+\end{minted}
+
+Connect or reset while holding the recovery or FEL button.
+Once the board has booted into FEL mode, we can detect the SPI NOR flash chip as follows:
+
+\begin{minted}{text}
+./sunxi-fel spiflash-info
+Manufacturer: Winbond (EFh), model: 40h, size: 16777216 bytes.
+\end{minted}
+
+Then we can write the \path{u-boot.bin}, \path{bzImage} and \path{initramfs.cpio.gz} images as follows:
+
+\begin{minted}{text}
+./sunxi-fel -p spiflash-write 0x000000 u-boot.bin
+./sunxi-fel -p spiflash-write 0x080000 bzImage
+./sunxi-fel -p spiflash-write 0x400000 initramfs.cpio.gz
+\end{minted}
 \end{document}