From 0fb4d67ccea7bd4b0d089340eaf20195f1651b16 Mon Sep 17 00:00:00 2001 From: "S.J.R. van Schaik" Date: Tue, 31 Oct 2017 11:56:01 +0100 Subject: [PATCH] stm32f0: stm32f1: gpio: rcc: set up timers for PWM --- source/platform/stm32f0/gpio.c | 13 +++++++++++++ source/platform/stm32f0/rcc.c | 6 ++++++ source/platform/stm32f1/gpio.c | 7 +++++++ source/platform/stm32f1/rcc.c | 1 + 4 files changed, 27 insertions(+) diff --git a/source/platform/stm32f0/gpio.c b/source/platform/stm32f0/gpio.c index c1de3d6..770746f 100644 --- a/source/platform/stm32f0/gpio.c +++ b/source/platform/stm32f0/gpio.c @@ -22,6 +22,19 @@ int gpio_init(void) gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO1); gpio_set_output_options(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO1); + /* Set up GPIOs for timers */ + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8); + gpio_set_af(GPIOA, GPIO_AF2, GPIO8); + + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO1); + gpio_set_af(GPIOA, GPIO_AF2, GPIO1); + + gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO4); + gpio_set_af(GPIOB, GPIO_AF1, GPIO4); + + gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO1); + gpio_set_af(GPIOB, GPIO_AF2, GPIO1); + return 0; } diff --git a/source/platform/stm32f0/rcc.c b/source/platform/stm32f0/rcc.c index 43347f3..5eb71a7 100644 --- a/source/platform/stm32f0/rcc.c +++ b/source/platform/stm32f0/rcc.c @@ -4,11 +4,17 @@ int rcc_init(void) { + rcc_clock_setup_in_hsi_out_48mhz(); + rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_SPI1); rcc_periph_clock_enable(RCC_USART1); rcc_periph_clock_enable(RCC_USART2); + rcc_periph_clock_enable(RCC_TIM1); + rcc_periph_clock_enable(RCC_TIM2); + rcc_periph_clock_enable(RCC_TIM3); + rcc_periph_clock_enable(RCC_TIM14); return 0; } diff --git a/source/platform/stm32f1/gpio.c b/source/platform/stm32f1/gpio.c index abf2116..03797eb 100644 --- a/source/platform/stm32f1/gpio.c +++ b/source/platform/stm32f1/gpio.c @@ -29,6 +29,13 @@ int gpio_init(void) gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO1); + /* Set up GPIOs for timers. */ + gpio_primary_remap(0, AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM2_PR1_CH3); + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM2_PR1_CH4); + return 0; } diff --git a/source/platform/stm32f1/rcc.c b/source/platform/stm32f1/rcc.c index e18f9f6..9297e29 100644 --- a/source/platform/stm32f1/rcc.c +++ b/source/platform/stm32f1/rcc.c @@ -10,6 +10,7 @@ int rcc_init(void) rcc_periph_clock_enable(RCC_SPI1); rcc_periph_clock_enable(RCC_USART1); rcc_periph_clock_enable(RCC_USART2); + rcc_periph_clock_enable(RCC_TIM2); return 0; }