upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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49 lines
1.2 KiB
49 lines
1.2 KiB
9 years ago
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __asm_arch_cpu_h
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#define __asm_arch_cpu_h
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/* CPU types */
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#define HASWELL_FAMILY_ULT 0x40650
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#define BROADWELL_FAMILY_ULT 0x306d0
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/* Supported CPUIDs */
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#define CPUID_HASWELL_A0 0x306c1
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#define CPUID_HASWELL_B0 0x306c2
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#define CPUID_HASWELL_C0 0x306c3
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#define CPUID_HASWELL_ULT_B0 0x40650
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#define CPUID_HASWELL_ULT 0x40651
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#define CPUID_HASWELL_HALO 0x40661
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#define CPUID_BROADWELL_C0 0x306d2
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#define CPUID_BROADWELL_D0 0x306d3
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#define CPUID_BROADWELL_E0 0x306d4
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/* Broadwell bus clock is fixed at 100MHz */
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#define BROADWELL_BCLK 100
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#define BROADWELL_FAMILY_ULT 0x306d0
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#define CORE_THREAD_COUNT_MSR 0x35
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define MSR_PKG_POWER_SKU 0x614
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#define MSR_DDR_RAPL_LIMIT 0x618
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#define MSR_VR_MISC_CONFIG2 0x636
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/* Latency times in units of 1024ns. */
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#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
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#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
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#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
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#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
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#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
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#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
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void cpu_set_power_limits(int power_limit_1_time);
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#endif
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