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/*
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* armboot - Startup Code for ARM926EJS CPU-core
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*
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* Copyright (c) 2003 Texas Instruments
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*
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* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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.globl _start
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_start:
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b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction:
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_software_interrupt:
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_prefetch_abort:
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_data_abort:
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_not_used:
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_irq:
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_fiq:
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.word infinite_loop
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infinite_loop:
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b infinite_loop
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* Below are the critical initializations already taken place in BootROM.
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* So, these are not taken care in Xloader
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* 1. Relocation to RAM
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* 2. Initializing stacks
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*
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*************************************************************************
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*/
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/*
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* the actual reset code
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*/
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reset:
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/*
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* Xloader has to return back to BootROM in a few cases.
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* eg. Ethernet boot, UART boot, USB boot
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* Saving registers for returning back
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*/
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stmdb sp!, {r0-r12,r14}
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bl cpu_init_crit
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/*
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* Clearing bss area is not done in Xloader.
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* BSS area lies in the DDR location which is not yet initialized
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* bss is assumed to be uninitialized.
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*/
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bl spl_boot
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ldmia sp!, {r0-r12,pc}
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* enable instruction cache
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*/
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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/*
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* Go setup Memory and board specific bits prior to relocation.
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*/
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stmdb sp!, {lr}
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bl lowlevel_init /* go setup pll,mux,memory */
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ldmia sp!, {pc}
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