upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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654 lines
26 KiB
654 lines
26 KiB
23 years ago
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#include <common.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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#include "atm.h"
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#include <linux/stddef.h>
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#define SYNC __asm__("sync")
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#define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
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#define FALSE 1
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#define TRUE 0
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#define OK 0
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#define ERROR -1
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struct atm_connection_t g_conn[NUM_CONNECTIONS] =
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{
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{ NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */
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};
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struct atm_driver_t g_atm =
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{
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FALSE, /* loaded */
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FALSE, /* started */
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NULL, /* csram */
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0, /* csram_size */
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NULL, /* am_top */
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NULL, /* ap_top */
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NULL, /* int_reload_ptr */
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NULL, /* int_serv_ptr */
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NULL, /* rbd_base_ptr */
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NULL, /* tbd_base_ptr */
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0 /* linerate */
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};
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char csram[1024]; /* more than enough for doing nothing*/
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int atmLoad(void);
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void atmUnload(void);
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int atmMemInit(void);
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void atmIntInit(void);
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void atmApcInit(void);
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void atmAmtInit(void);
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void atmCpmInit(void);
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void atmUtpInit(void);
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/*****************************************************************************
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*
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* FUNCTION NAME: atmLoad
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*
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* DESCRIPTION: Basic ATM initialization.
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*
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* PARAMETERS: none
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*
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* RETURNS: OK or ERROR
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*
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****************************************************************************/
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int atmLoad()
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
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volatile iop8xx_t *iop = &immap->im_ioport;
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timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
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immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
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iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
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if ( atmMemInit() != OK ) return ERROR;
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atmIntInit();
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atmApcInit();
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atmAmtInit();
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atmCpmInit();
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atmUtpInit();
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g_atm.loaded = TRUE;
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return OK;
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}
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/*****************************************************************************
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*
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* FUNCTION NAME: atmUnload
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*
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* DESCRIPTION: Disables ATM and UTOPIA.
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*
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* PARAMETERS: none
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*
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* RETURNS: void
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*
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****************************************************************************/
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void atmUnload()
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
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volatile iop8xx_t *iop = &immap->im_ioport;
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timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
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immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
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iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
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g_atm.loaded = FALSE;
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}
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/*****************************************************************************
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*
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* FUNCTION NAME: atmMemInit
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*
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* DESCRIPTION:
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*
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* The ATM driver uses the following resources:
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*
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* A. Memory in DPRAM to hold
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*
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* 1/ CT = Connection Table ( RCT & TCT )
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* 2/ TCTE = Transmit Connection Table Extension
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* 3/ MPHYPT = Multi-PHY Pointing Table
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* 4/ APCP = APC Parameter Table
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* 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
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* 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
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* 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
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* 8/ TQ = Transmit Queue
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* 9/ AM = Address Matching Table
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* 10/ AP = Address Pointing Table
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*
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* B. Memory in cache safe RAM to hold
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*
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* 1/ INT = Interrupt Queue
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* 2/ RBD = Receive Buffer Descriptors
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* 3/ TBD = Transmit Buffer Descriptors
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*
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* This function
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* 1. clears the ATM DPRAM area,
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* 2. Allocates and clears cache safe memory,
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* 3. Initializes 'g_conn'.
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*
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* PARAMETERS: none
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*
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* RETURNS: OK or ERROR
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*
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****************************************************************************/
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int atmMemInit()
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{
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int i;
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unsigned immr = CFG_IMMR;
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int total_num_rbd = 0;
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int total_num_tbd = 0;
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memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
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g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
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for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
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total_num_rbd += g_conn[i].num_rbd;
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total_num_tbd += g_conn[i].num_tbd;
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}
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g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
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g_atm.csram = &csram[0];
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memset(&(g_atm.csram), 0x00, g_atm.csram_size);
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g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4);
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g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
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g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
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g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
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g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
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g_conn[0].ct_ptr = CT_PTR(immr);
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g_conn[0].tcte_ptr = TCTE_PTR(immr);
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return OK;
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}
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/*****************************************************************************
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*
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* FUNCTION NAME: atmIntInit
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*
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* DESCRIPTION:
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*
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* Initialization of the MPC860 ESAR Interrupt Queue.
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* This function
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* - clears all entries in the INT,
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* - sets the WRAP bit of the last INT entry,
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* - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
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* to the first INT entry.
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*
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* PARAMETERS: none
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*
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* RETURNS: void
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*
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* REMARKS:
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*
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* - The INT resides in external cache safe memory.
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* - The base address of the INT is stored in g_atm.int_reload_ptr.
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* - The number of entries in the INT is given by NUM_INT_ENTRIES.
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* - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
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*
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****************************************************************************/
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void atmIntInit()
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{
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int i;
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for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
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g_atm.int_reload_ptr[i] = INT_WRAP;
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g_atm.int_serv_ptr = g_atm.int_reload_ptr;
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}
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/*****************************************************************************
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*
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* FUNCTION NAME: atmApcInit
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*
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* DESCRIPTION:
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*
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* This function initializes the following ATM Pace Controller related
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* data structures:
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*
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* - 1 MPHY Pointing Table (contains only one entry)
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* - 3 APC Parameter Tables (one PHY with 3 priorities)
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* - 3 APC Tables (one table for each priority)
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* - 1 Transmit Queue (one transmit queue per PHY)
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*
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* PARAMETERS: none
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*
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* RETURNS: void
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*
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****************************************************************************/
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void atmApcInit()
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{
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int i;
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/* unsigned immr = CFG_IMMR; */
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uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR);
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struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR);
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uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR);
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uint16 * tq_ptr = TQ_PTR(CFG_IMMR);
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/***************************************************/
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/* Initialize MPHY Pointing Table (only one entry) */
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/***************************************************/
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*mphypt_ptr = APCP_BASE;
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/********************************************/
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/* Initialize APC parameters for priority 1 */
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/********************************************/
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apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
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apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
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apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE;
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apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
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apcp_ptr->etqbase = TQ_BASE;
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apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
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apcp_ptr->etqaptr = TQ_BASE;
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apcp_ptr->etqtptr = TQ_BASE;
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apcp_ptr->apc_mi = 8;
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apcp_ptr->ncits = 0x0100; /* NCITS = 1 */
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apcp_ptr->apcnt = 0;
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apcp_ptr->reserved1 = 0;
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apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */
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apcp_ptr->ptp_counter = 0;
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apcp_ptr->ptp_txch = 0;
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apcp_ptr->reserved2 = 0;
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/***************************************************/
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/* Initialize APC Tables with empty slots (0xFFFF) */
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/***************************************************/
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for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
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/************************/
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/* Clear Transmit Queue */
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/************************/
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for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
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}
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/*****************************************************************************
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*
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* FUNCTION NAME: atmAmtInit
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*
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* DESCRIPTION:
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*
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* This function clears the first entry in the Address Matching Table and
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* lets the first entry in the Address Pointing table point to the first
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* entry in the TCT table (i.e. the raw cell channel).
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*
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* PARAMETERS: none
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*
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* RETURNS: void
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*
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* REMARKS:
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*
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* The values for the AMBASE, AMEND and APBASE registers in SAR parameter
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* RAM are initialized by atmCpmInit().
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*
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****************************************************************************/
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void atmAmtInit()
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{
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unsigned immr = CFG_IMMR;
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g_atm.am_top = AM_PTR(immr);
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g_atm.ap_top = AP_PTR(immr);
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*(g_atm.ap_top--) = CT_BASE;
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*(g_atm.am_top--) = 0;
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}
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/*****************************************************************************
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*
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* FUNCTION NAME: atmCpmInit
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*
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* DESCRIPTION:
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*
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* This function initializes the Utopia Interface Parameter RAM Map
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* (SCC4, ATM Protocol) of the Communication Processor Modudule.
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*
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* PARAMETERS: none
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*
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* RETURNS: void
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*
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****************************************************************************/
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void atmCpmInit()
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{
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unsigned immr = CFG_IMMR;
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memset((char *)immr + 0x3F00, 0x00, 0xC0);
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/*-----------------------------------------------------------------*/
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/* RBDBASE - Receive buffer descriptors base address */
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/* The RBDs reside in cache safe external memory. */
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/*-----------------------------------------------------------------*/
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*RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
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/*-----------------------------------------------------------------*/
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/* SRFCR - SAR receive function code */
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/* 0-2 rsvd = 000 */
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/* 3-4 BO = 11 Byte ordering (big endian). */
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/* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
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/* when the SDMA channel accesses memory. */
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/*-----------------------------------------------------------------*/
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*SRFCR(immr) = 0x18;
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/*-----------------------------------------------------------------*/
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/* SRSTATE - SAR receive status */
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/* 0 EXT = 0 Extended mode off. */
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/* 1 ACP = 0 Valid only if EXT = 1. */
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/* 2 EC = 0 Standard 53-byte ATM cell. */
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/* 3 SNC = 0 In sync. Must be set to 0 during initialization. */
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/* 4 ESAR = 1 Enhanced SAR functionality enabled. */
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/* 5 MCF = 1 Management Cell Filter active. */
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/* 6 SER = 0 UTOPIA mode. */
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/* 7 MPY = 1 Multiple PHY mode. */
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/*-----------------------------------------------------------------*/
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*SRSTATE(immr) = 0x0D;
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/*-----------------------------------------------------------------*/
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/* MRBLR - Maximum receive buffer length register. */
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/* Must be cleared for ATM operation (see also SMRBLR). */
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/*-----------------------------------------------------------------*/
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*MRBLR(immr) = 0;
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/*-----------------------------------------------------------------*/
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/* RSTATE - SCC internal receive state parameters */
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/* The first byte must be initialized with the value of SRFCR. */
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/*-----------------------------------------------------------------*/
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|
|
*RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* STFCR - SAR transmit function code */
|
||
|
|
/* 0-2 rsvd = 000 */
|
||
|
|
/* 3-4 BO = 11 Byte ordering (big endian). */
|
||
|
|
/* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
|
||
|
|
/* when the SDMA channel accesses memory. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*STFCR(immr) = 0x18;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* SRSTATE - SAR transmit status */
|
||
|
|
/* 0 EXT = 0 : Extended mode off */
|
||
|
|
/* 1 rsvd = 0 : */
|
||
|
|
/* 2 EC = 0 : Standard 53-byte ATM cell */
|
||
|
|
/* 3 rsvd = 0 : */
|
||
|
|
/* 4 ESAR = 1 : Enhanced SAR functionality enabled */
|
||
|
|
/* 5 rsvd = 0 : */
|
||
|
|
/* 6 SER = 0 : UTOPIA mode */
|
||
|
|
/* 7 MPY = 1 : Multiple PHY mode */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*STSTATE(immr) = 0x09;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* TBDBASE - Transmit buffer descriptors base address */
|
||
|
|
/* The TBDs reside in cache safe external memory. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* TSTATE - SCC internal transmit state parameters */
|
||
|
|
/* The first byte must be initialized with the value of STFCR. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* CTBASE - Connection table base address */
|
||
|
|
/* Offset from the beginning of DPRAM (64-byte aligned). */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*CTBASE(immr) = CT_BASE;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* INTBASE - Interrupt queue base pointer. */
|
||
|
|
/* The interrupt queue resides in cache safe external memory. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* INTPTR - Pointer into interrupt queue. */
|
||
|
|
/* Initialize to INTBASE. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*INTPTR(immr) = *INTBASE(immr);
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* C_MASK - Constant mask for CRC32 */
|
||
|
|
/* Must be initialized to 0xDEBB20E3. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*C_MASK(immr) = 0xDEBB20E3;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* INT_ICNT - Interrupt threshold value */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*INT_ICNT(immr) = 1;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* INT_CNT - Interrupt counter */
|
||
|
|
/* Initalize to INT_ICNT. Decremented for each interrupt entry */
|
||
|
|
/* reported in the interrupt queue. On zero an interrupt is */
|
||
|
|
/* signaled to the host by setting the GINT bit in the event */
|
||
|
|
/* register. The counter is reinitialized with INT_ICNT. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*INT_CNT(immr) = *INT_ICNT(immr);
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* SMRBLR - SAR maximum receive buffer length register. */
|
||
|
|
/* Must be a multiple of 48 bytes. Common for all ATM connections. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*SMRBLR(immr) = SAR_RXB_SIZE;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* APCST - APC status register. */
|
||
|
|
/* 0 rsvd 0 */
|
||
|
|
/* 1-2 CSER 11 Initialize with the same value as NSER. */
|
||
|
|
/* 3-4 NSER 11 Next serial or UTOPIA channel. */
|
||
|
|
/* 5-7 rsvd 000 */
|
||
|
|
/* 8-10 rsvd 000 */
|
||
|
|
/* 11 rsvd 0 */
|
||
|
|
/* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */
|
||
|
|
/* 13 DIS 0 APC disable. Must be initiazed to 0. */
|
||
|
|
/* 14 PL2 0 Not used. */
|
||
|
|
/* 15 MPY 1 Multiple PHY mode on. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*APCST(immr) = 0x7809;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* APCPTR - Pointer to the APC parameter table */
|
||
|
|
/* In MPHY master mode this parameter points to the MPHY pointing */
|
||
|
|
/* table. 2-byte aligned. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*APCPTR(immr) = MPHYPT_BASE;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* HMASK - Header mask */
|
||
|
|
/* Each incoming cell is masked with HMASK before being compared */
|
||
|
|
/* to the entries in the address matching table. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*HMASK(immr) = AM_HMASK;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* AMBASE - Address matching table base address */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*AMBASE(immr) = AM_BASE;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* AMEND - Address matching table end address */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*AMEND(immr) = AM_BASE;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* APBASE - Address pointing table base address */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*APBASE(immr) = AP_BASE;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* MPHYST - MPHY status register */
|
||
|
|
/* 0-1 rsvd 00 */
|
||
|
|
/* 2-6 NMPHY 00000 1 PHY */
|
||
|
|
/* 7-9 rsvd 000 */
|
||
|
|
/* 10-14 CMPHY 00000 Initialize with same value as NMPHY */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*MPHYST(immr) = 0x0000;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* TCTEBASE - Transmit connection table extension base address */
|
||
|
|
/* Offset from the beginning of DPRAM (32-byte aligned). */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
*TCTEBASE(immr) = TCTE_BASE;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* Clear not used registers. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
}
|
||
|
|
|
||
|
|
/*****************************************************************************
|
||
|
|
*
|
||
|
|
* FUNCTION NAME: atmUtpInit
|
||
|
|
*
|
||
|
|
* DESCRIPTION:
|
||
|
|
*
|
||
|
|
* This function initializes the ATM interface for
|
||
|
|
*
|
||
|
|
* - UTOPIA mode
|
||
|
|
* - muxed bus
|
||
|
|
* - master operation
|
||
|
|
* - multi PHY (because of a bug in the MPC860P rev. E.0)
|
||
|
|
* - internal clock = SYSCLK / 2
|
||
|
|
*
|
||
|
|
* EXTERNAL EFFECTS:
|
||
|
|
*
|
||
|
|
* After calling this function, the MPC860ESAR UTOPIA bus is
|
||
|
|
* active and uses the following ports/pins:
|
||
|
|
*
|
||
|
|
* Port Pin Signal Description
|
||
|
|
* ------ --- ------- -------------------------------------------
|
||
|
|
* PB[15] R17 TxClav Transmit cell available input/output signal
|
||
|
|
* PC[15] D16 RxClav Receive cell available input/output signal
|
||
|
|
* PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal
|
||
|
|
* PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal
|
||
|
|
* PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal
|
||
|
|
* PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal
|
||
|
|
* PD[11] T16 RXENB Receive enable input/output signal
|
||
|
|
* PD[10] W18 TXENB Transmit enable input/output signal
|
||
|
|
* PD[9] V17 UTPCLK UTOPIA clock input/output signal
|
||
|
|
* PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal
|
||
|
|
* PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal
|
||
|
|
* PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal
|
||
|
|
* PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal
|
||
|
|
* PD[3] W16 SOC Start of cell input/output signal
|
||
|
|
*
|
||
|
|
* PARAMETERS: none
|
||
|
|
*
|
||
|
|
* RETURNS: void
|
||
|
|
*
|
||
|
|
* REMARK:
|
||
|
|
*
|
||
|
|
* The ATM parameters and data structures must be configured before
|
||
|
|
* initializing the UTOPIA port. The UTOPIA port activates immediately
|
||
|
|
* upon initialization, and if its associated data structures are not
|
||
|
|
* initialized, the CPM will lock up.
|
||
|
|
*
|
||
|
|
****************************************************************************/
|
||
|
|
void atmUtpInit()
|
||
|
|
{
|
||
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||
|
|
volatile iop8xx_t *iop = &immap->im_ioport;
|
||
|
|
volatile car8xx_t *car = &immap->im_clkrst;
|
||
|
|
volatile cpm8xx_t *cpm = &immap->im_cpm;
|
||
|
|
int flag;
|
||
|
|
|
||
|
|
flag = disable_interrupts();
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* SCCR - System Clock Control Register */
|
||
|
|
/* */
|
||
|
|
/* The UTOPIA clock can be selected to be internal clock or */
|
||
|
|
/* external clock (selected by the UTOPIA mode register). */
|
||
|
|
/* In case of internal clock, the UTOPIA clock is derived from */
|
||
|
|
/* the system frequency divided by two dividers. */
|
||
|
|
/* Bits 27-31 of the SCCR register are defined to control the */
|
||
|
|
/* UTOPIA clock. */
|
||
|
|
/* */
|
||
|
|
/* SCCR[27:29] DFUTP Division factor. Divide the system clock */
|
||
|
|
/* by 2^DFUTP. */
|
||
|
|
/* SCCR[30:31] DFAUTP Additional division factor. Divide the */
|
||
|
|
/* system clock by the following value: */
|
||
|
|
/* 00 = divide by 1 */
|
||
|
|
/* 00 = divide by 3 */
|
||
|
|
/* 10 = divide by 5 */
|
||
|
|
/* 11 = divide by 7 */
|
||
|
|
/* */
|
||
|
|
/* Note that the UTOPIA clock must be programmed as to operate */
|
||
|
|
/* within the range SYSCLK/10 .. 50Mhz. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
car->car_sccr &= 0xFFFFFFE0;
|
||
|
|
car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* RCCR - RISC Controller Configuration Register */
|
||
|
|
/* */
|
||
|
|
/* RCCR[8] DR1M IDMA Request 0 Mode */
|
||
|
|
/* 0 = edge sensitive */
|
||
|
|
/* 1 = level sensitive */
|
||
|
|
/* RCCR[9] DR0M IDMA Request 0 Mode */
|
||
|
|
/* 0 = edge sensitive */
|
||
|
|
/* 1 = level sensitive */
|
||
|
|
/* RCCR[10:11] DRQP IDMA Request Priority */
|
||
|
|
/* 00 = IDMA req. have more prio. than SCCs */
|
||
|
|
/* 01 = IDMA req. have less prio. then SCCs */
|
||
|
|
/* 10 = IDMA requests have the lowest prio. */
|
||
|
|
/* 11 = reserved */
|
||
|
|
/* */
|
||
|
|
/* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
|
||
|
|
/* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
|
||
|
|
/* higher priority. */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
cpm->cp_rccr &= 0xFF0F;
|
||
|
|
cpm->cp_rccr |= 0x00D0;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* Port B - TxClav Signal */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
|
||
|
|
cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* UTOPIA Mode Register */
|
||
|
|
/* */
|
||
|
|
/* - muxed bus (master operation only) */
|
||
|
|
/* - multi PHY (because of a bug in the MPC860P rev.E.0) */
|
||
|
|
/* - internal clock */
|
||
|
|
/* - no loopback */
|
||
|
|
/* - do no activate statistical counters */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
iop->utmode = 0x00000004; SYNC;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* Port D - UTOPIA Data and Control Signals */
|
||
|
|
/* */
|
||
|
|
/* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */
|
||
|
|
/* 11 RXENB UTOPIA receive enable input/output signal */
|
||
|
|
/* 10 TXENB UTOPIA transmit enable input/output signal */
|
||
|
|
/* 9 TUPCLK UTOPIA clock input/output signal */
|
||
|
|
/* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */
|
||
|
|
/* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */
|
||
|
|
/* 3 SOC UTOPIA Start of cell input/output signal */
|
||
|
|
/* 2 Reserved */
|
||
|
|
/* 1 Enable UTOPIA mode */
|
||
|
|
/* 0 Enable SAR */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
iop->iop_pdpar |= 0xDF7F; SYNC;
|
||
|
|
iop->iop_pddir &= 0x2080; SYNC;
|
||
|
|
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
/* Port C - RxClav Signal */
|
||
|
|
/*-----------------------------------------------------------------*/
|
||
|
|
iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */
|
||
|
|
iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */
|
||
|
|
iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */
|
||
|
|
|
||
|
|
if (flag)
|
||
|
|
enable_interrupts();
|
||
|
|
}
|