upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.4 KiB
149 lines
3.4 KiB
17 years ago
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#include <config.h>
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#include <mpc85xx.h>
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#include <version.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/* To boot secondary cpus, we need a place for them to start up.
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* Normally, they start at 0xfffffffc, but that's usually the
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* firmware, and we don't want to have to run the firmware again.
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* Instead, the primary cpu will set the BPTR to point here to
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* this page. We then set up the core, and head to
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* start_secondary. Note that this means that the code below
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* must never exceed 1023 instructions (the branch at the end
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* would then be the 1024th).
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*/
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.globl __secondary_start_page
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.align 12
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__secondary_start_page:
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/* First do some preliminary setup */
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lis r3, HID0_EMCP@h /* enable machine check */
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ori r3,r3,HID0_TBEN@l /* enable Timebase */
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#ifdef CONFIG_PHYS_64BIT
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ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
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#endif
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mtspr SPRN_HID0,r3
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li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
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mtspr SPRN_HID1,r3
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/* Enable branch prediction */
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li r3,0x201
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mtspr SPRN_BUCSR,r3
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/* Enable/invalidate the I-Cache */
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mfspr r0,SPRN_L1CSR1
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ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
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mtspr SPRN_L1CSR1,r0
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isync
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/* Enable/invalidate the D-Cache */
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mfspr r0,SPRN_L1CSR0
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ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
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msync
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isync
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mtspr SPRN_L1CSR0,r0
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isync
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#define toreset(x) (x - __secondary_start_page + 0xfffff000)
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/* get our PIR to figure out our table entry */
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lis r3,toreset(__spin_table)@h
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ori r3,r3,toreset(__spin_table)@l
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/* r9 has the base address for the entry */
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mfspr r0,SPRN_PIR
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mr r4,r0
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slwi r8,r4,4
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slwi r9,r4,3
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add r8,r8,r9
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add r9,r3,r8
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#define EPAPR_MAGIC (0x65504150)
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#define ENTRY_ADDR 0
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#define ENTRY_PIR 4
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#define ENTRY_R3 8
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#define ENTRY_R4 12
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#define ENTRY_R6 16
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#define ENTRY_R7 20
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/* setup the entry */
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li r4,0
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li r8,1
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lis r6,EPAPR_MAGIC@h
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ori r6,r6,EPAPR_MAGIC@l
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stw r0,ENTRY_PIR(r9)
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stw r8,ENTRY_ADDR(r9)
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stw r4,ENTRY_R3(r9)
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stw r4,ENTRY_R4(r9)
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stw r6,ENTRY_R6(r9)
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stw r4,ENTRY_R7(r9)
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/* spin waiting for addr */
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1: lwz r4,ENTRY_ADDR(r9)
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andi. r11,r4,1
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bne 1b
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/* setup branch addr */
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mtctr r4
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/* mark the entry as released */
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li r8,3
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stw r8,ENTRY_ADDR(r9)
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/* mask by ~64M to setup our tlb we will jump to */
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rlwinm r8,r4,0,0,5
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/* setup r3, r5, r6, r7 */
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lwz r3,ENTRY_R3(r9)
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lwz r4,ENTRY_R4(r9)
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li r5,0
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lwz r6,ENTRY_R6(r9)
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lwz r7,ENTRY_R7(r9)
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/* load up the pir */
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lwz r0,ENTRY_PIR(r9)
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mtspr SPRN_PIR,r0
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mfspr r0,SPRN_PIR
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stw r0,ENTRY_PIR(r9)
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/*
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* Coming here, we know the cpu has one TLB mapping in TLB1[0]
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* which maps 0xfffff000-0xffffffff one-to-one. We set up a
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* second mapping that maps addr 1:1 for 64M, and then we jump to
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* addr
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*/
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lis r9,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
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mtspr SPRN_MAS0,r9
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lis r9,(MAS1_VALID|MAS1_IPROT)@h
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ori r9,r9,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
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mtspr SPRN_MAS1,r9
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/* WIMGE = 0b00000 for now */
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mtspr SPRN_MAS2,r8
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ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR)
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mtspr SPRN_MAS3,r8
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tlbwe
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/* Now we have another mapping for this page, so we jump to that
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* mapping
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*/
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bctr
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.align 3
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.globl __spin_table
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__spin_table:
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.space CONFIG_NR_CPUS*24
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/* Fill in the empty space. The actual reset vector is
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* the last word of the page */
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__secondary_start_code_end:
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.space 4092 - (__secondary_start_code_end - __secondary_start_page)
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__secondary_reset_vector:
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b __secondary_start_page
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