upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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54 lines
1.4 KiB
54 lines
1.4 KiB
14 years ago
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* Authors: Chunhe Lan <b25806@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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*/
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#ifndef __BCSR_H_
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#define __BCSR_H_
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#include <common.h>
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/*
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* BCSR Bit definitions
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* BCSR 15 *
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0 device insertion oriention
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1 stack processor present
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2 power supply shut down/normal operation
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3 I2C bus0 drive enable
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4 reserved
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5:7 I2C bus0 select
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5 - I2C_BUS_0_SS0
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6 - I2C_BUS_0_SS1
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7 - I2C_BUS_0_SS2
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*/
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/* BCSR register base address is 0xFX000020 */
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#define BCSR_BASE_REG_OFFSET 0x20
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#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET)
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#define BCSR15_DEV_INS_ORI 0x80
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#define BCSR15_STACK_PRO_PRE 0x40
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#define BCSR15_POWER_SUPPLY 0x20
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#define BCSR15_I2C_BUS0_EN 0x10
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#define BCSR15_I2C_BUS0_SEG0 0x00
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#define BCSR15_I2C_BUS0_SEG1 0x04
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#define BCSR15_I2C_BUS0_SEG2 0x02
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#define BCSR15_I2C_BUS0_SEG3 0x06
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#define BCSR15_I2C_BUS0_SEG4 0x01
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#define BCSR15_I2C_BUS0_SEG5 0x05
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#define BCSR15_I2C_BUS0_SEG6 0x03
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#define BCSR15_I2C_BUS0_SEG7 0x07
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#define BCSR15_I2C_BUS0_SEG_CLR 0x07
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#define BCSR19_SGMII_SEL_L 0x01
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/*BCSR Utils functions*/
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void fixup_i2c_bus0_sel_seg0(void);
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#endif /* __BCSR_H_ */
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