upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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294 lines
11 KiB
294 lines
11 KiB
21 years ago
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/* PCI.h - PCI functions header file */
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/* Copyright - Galileo technology. */
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#ifndef __INCpcih
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#define __INCpcih
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/* includes */
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#include"core.h"
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#include"memory.h"
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/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
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#define PCI_MAX_DEVICES 22
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/* Macros */
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/* The next Macros configurate the initiator board (SELF) or any any agent on
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the PCI to become: MASTER, response to MEMORY transactions , response to
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IO transactions or TWO both MEMORY_IO transactions. Those configuration
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are for both PCI0 and PCI1. */
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#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
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PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
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pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
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#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
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PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
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pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
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#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
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PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
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pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
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#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \
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PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
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pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
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#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \
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PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
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pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
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#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \
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PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
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pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
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#define MASTER_ENABLE BIT2
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#define MEMORY_ENABLE BIT1
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#define I_O_ENABLE BIT0
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#define SELF 32
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/* Agent on the PCI bus may have up to 6 BARS. */
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#define BAR0 0x10
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#define BAR1 0x14
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#define BAR2 0x18
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#define BAR3 0x1c
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#define BAR4 0x20
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#define BAR5 0x24
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#define BAR_SEL_MEM_IO BIT0
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#define BAR_MEM_TYPE_32_BIT NO_BIT
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#define BAR_MEM_TYPE_BELOW_1M BIT1
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#define BAR_MEM_TYPE_64_BIT BIT2
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#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2)
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#define BAR_MEM_TYPE_MASK (BIT1 | BIT2)
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#define BAR_PREFETCHABLE BIT3
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#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3)
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/* Defines for the access regions. */
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#define PREFETCH_ENABLE BIT12
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#define PREFETCH_DISABLE NO_BIT
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#define DELAYED_READ_ENABLE BIT13
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/* #define CACHING_ENABLE BIT14 */
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/* aggressive prefetch: PCI slave prefetch two burst in advance*/
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#define AGGRESSIVE_PREFETCH BIT16
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/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
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#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
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/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
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#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
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#define MAX_BURST_4 NO_BIT
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#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
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#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
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#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
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#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
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#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
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#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
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#define PCI_ACCESS_PROTECT BIT28
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#define PCI_WRITE_PROTECT BIT29
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/* typedefs */
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typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
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REGION6,REGION7} PCI_ACCESS_REGIONS;
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typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
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typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
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typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
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PCI_SNOOP_TYPE;
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typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
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PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
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PCI_SNOOP_REGION;
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typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
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typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
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PCI_REGION2,PCI_REGION3,
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PCI_IO}
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PCI_REGION;
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/*ronen 7/Dec/03 */
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typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
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PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
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PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
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PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
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PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
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PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
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PCI_LAST_BAR} PCI_INTERNAL_BAR;
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typedef struct pciBar {
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unsigned int detectBase;
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unsigned int base;
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unsigned int size;
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unsigned int type;
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} PCI_BAR;
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typedef struct pciDevice {
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PCI_HOST host;
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char type[40];
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unsigned int deviceNum;
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unsigned int venID;
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unsigned int deviceID;
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PCI_BAR bar[6];
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} PCI_DEVICE;
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typedef struct pciSelfBars {
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unsigned int SCS0Base;
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unsigned int SCS0Size;
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unsigned int SCS1Base;
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unsigned int SCS1Size;
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unsigned int SCS2Base;
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unsigned int SCS2Size;
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unsigned int SCS3Base;
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unsigned int SCS3Size;
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unsigned int internalMemBase;
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unsigned int internalIOBase;
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unsigned int CS0Base;
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unsigned int CS0Size;
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unsigned int CS1Base;
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unsigned int CS1Size;
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unsigned int CS2Base;
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unsigned int CS2Size;
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unsigned int CS3Base;
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unsigned int CS3Size;
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unsigned int CSBootBase;
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unsigned int CSBootSize;
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unsigned int P2PMem0Base;
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unsigned int P2PMem0Size;
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unsigned int P2PMem1Base;
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unsigned int P2PMem1Size;
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unsigned int P2PIOBase;
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unsigned int P2PIOSize;
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unsigned int CPUBase;
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unsigned int CPUSize;
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} PCI_SELF_BARS;
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/* read/write configuration registers on local PCI bus. */
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void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
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unsigned int pciDevNum, unsigned int data);
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unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
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unsigned int pciDevNum);
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/* read/write configuration registers on another PCI bus. */
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void pciOverBridgeWriteConfigReg(PCI_HOST host,
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unsigned int regOffset,
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unsigned int pciDevNum,
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unsigned int busNum,unsigned int data);
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unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
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unsigned int regOffset,
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unsigned int pciDevNum,
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unsigned int busNum);
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/* Performs full scane on both PCI and returns all detail possible on the
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agents which exist on the bus. */
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void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
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unsigned int numberOfElment);
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/* Master`s memory space */
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bool pciMapSpace(PCI_HOST host, PCI_REGION region,
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unsigned int remapBase,
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unsigned int deviceBase,
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unsigned int deviceLength);
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unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
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unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
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/* Slave`s memory space */
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void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
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unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
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#if 0 /* GARBAGE routines - dont use till they get cleaned up */
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void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
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void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
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void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
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void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
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void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
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void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
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void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
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unsigned int pci0Dev0Length);
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void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
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unsigned int pci1Dev0Length);
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void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
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unsigned int pci0Dev1Length);
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void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
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unsigned int pci1Dev1Length);
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void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
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unsigned int pci0Dev2Length);
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void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
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unsigned int pci1Dev2Length);
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void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
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unsigned int pci0Dev3Length);
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void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
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unsigned int pci1Dev3Length);
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void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
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unsigned int pci0DevBootLength);
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void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
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unsigned int pci1DevBootLength);
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void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
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unsigned int pci0P2pMem0Length);
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void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
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unsigned int pci1P2pMem0Length);
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void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
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unsigned int pci0P2pMem1Length);
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void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
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unsigned int pci1P2pMem1Length);
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void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
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unsigned int pci0P2pIoLength);
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void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
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unsigned int pci1P2pIoLength);
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void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
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void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
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#endif
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/* PCI region options */
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bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
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unsigned int features, unsigned int baseAddress,
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unsigned int regionLength);
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void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
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/* PCI arbiter */
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bool pciArbiterEnable(PCI_HOST host);
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bool pciArbiterDisable(PCI_HOST host);
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bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
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PCI_AGENT_PRIO externalAgent0,
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PCI_AGENT_PRIO externalAgent1,
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PCI_AGENT_PRIO externalAgent2,
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PCI_AGENT_PRIO externalAgent3,
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PCI_AGENT_PRIO externalAgent4,
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PCI_AGENT_PRIO externalAgent5);
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bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
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PCI_AGENT_PRIO externalAgent0,
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PCI_AGENT_PRIO externalAgent1,
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PCI_AGENT_PRIO externalAgent2,
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PCI_AGENT_PRIO externalAgent3,
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PCI_AGENT_PRIO externalAgent4,
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PCI_AGENT_PRIO externalAgent5);
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bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
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PCI_AGENT_PARK externalAgent0,
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PCI_AGENT_PARK externalAgent1,
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PCI_AGENT_PARK externalAgent2,
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PCI_AGENT_PARK externalAgent3,
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PCI_AGENT_PARK externalAgent4,
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PCI_AGENT_PARK externalAgent5);
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bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
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bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
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/* PCI-to-PCI (P2P) */
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bool pciP2PConfig(PCI_HOST host,
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unsigned int SecondBusLow,unsigned int SecondBusHigh,
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unsigned int busNum,unsigned int devNum);
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/* PCI Cache-coherency */
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bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
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PCI_SNOOP_TYPE snoopType,
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unsigned int baseAddress,
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unsigned int regionLength);
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PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
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#endif /* __INCpcih */
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