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/************************************************************************
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*
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* cplb.h
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*
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* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
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*
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************************************************************************/
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/* Defines necessary for cplb initialisation routines. */
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#ifndef _CPLB_H
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#define _CPLB_H
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#define CONFIG_BLKFIN_WT
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#define CPLB_ENABLE_ICACHE_P 0
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#define CPLB_ENABLE_DCACHE_P 1
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#define CPLB_ENABLE_DCACHE2_P 2
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#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
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#define CPLB_ENABLE_ICPLBS_P 4
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#define CPLB_ENABLE_DCPLBS_P 5
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#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
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#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
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#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
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#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
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#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
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#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
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#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
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CPLB_ENABLE_ICPLBS | \
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CPLB_ENABLE_DCPLBS
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#define CPLB_RELOADED 0x0000
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#define CPLB_NO_UNLOCKED 0x0001
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#define CPLB_NO_ADDR_MATCH 0x0002
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#define CPLB_PROT_VIOL 0x0003
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#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
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#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
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#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
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#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
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#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
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#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
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#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
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/* Data Attibutes*/
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#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
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#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
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/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
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#define ANOMALY_05000158 0x200
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#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
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#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
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#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
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#else /*Write Through */
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#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
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#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
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#endif
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#if defined(CONFIG_BF561)
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#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */
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#else
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#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */
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#endif
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#endif /* _CPLB_H */
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