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/*
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* MCF5272 Internal Memory Map
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*
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* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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* 2006 Zachary P. Landau <zachary.landau@labxtechnologies.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5271__
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#define __IMMAP_5271__
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#define MMAP_SCM (CFG_MBAR + 0x00000000)
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#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
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#define MMAP_FBCS (CFG_MBAR + 0x00000080)
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#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
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#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
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#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
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#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
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#define MMAP_UART0 (CFG_MBAR + 0x00000200)
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#define MMAP_UART1 (CFG_MBAR + 0x00000240)
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#define MMAP_UART2 (CFG_MBAR + 0x00000280)
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#define MMAP_I2C (CFG_MBAR + 0x00000300)
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#define MMAP_QSPI (CFG_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
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#define MMAP_FEC (CFG_MBAR + 0x00001000)
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#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
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#define MMAP_GPIO (CFG_MBAR + 0x00100000)
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#define MMAP_CCM (CFG_MBAR + 0x00110000)
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#define MMAP_PLL (CFG_MBAR + 0x00120000)
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#define MMAP_EPORT (CFG_MBAR + 0x00130000)
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#define MMAP_WDOG (CFG_MBAR + 0x00140000)
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#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
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#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
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#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
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#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
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#define MMAP_MDHA (CFG_MBAR + 0x00190000)
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#define MMAP_RNG (CFG_MBAR + 0x001A0000)
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#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
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#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
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#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
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#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
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/* Interrupt module registers */
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typedef struct int0_ctrl {
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/* Interrupt Controller 0 */
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u32 iprh0; /* 0x00 Pending Register High */
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u32 iprl0; /* 0x04 Pending Register Low */
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u32 imrh0; /* 0x08 Mask Register High */
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u32 imrl0; /* 0x0C Mask Register Low */
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u32 frch0; /* 0x10 Force Register High */
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u32 frcl0; /* 0x14 Force Register Low */
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u8 irlr; /* 0x18 */
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u8 iacklpr; /* 0x19 */
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u16 res1[19]; /* 0x1a - 0x3c */
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u8 icr0[64]; /* 0x40 - 0x7F Control registers */
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u32 res3[24]; /* 0x80 - 0xDF */
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u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
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u8 res4[3]; /* 0xE1 - 0xE3 */
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u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
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u8 res5[3]; /* 0xE5 - 0xE7 */
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u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
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u8 res6[3]; /* 0xE9 - 0xEB */
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u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
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u8 res7[3]; /* 0xED - 0xEF */
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u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
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u8 res8[3]; /* 0xF1 - 0xF3 */
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u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
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u8 res9[3]; /* 0xF5 - 0xF7 */
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u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
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u8 resa[3]; /* 0xF9 - 0xFB */
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u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
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u8 resb[3]; /* 0xFD - 0xFF */
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} int0_t;
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#endif /* __IMMAP_5271__ */
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