upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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162 lines
4.7 KiB
162 lines
4.7 KiB
17 years ago
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts shamelesly stolen from Linux Kernel source tree.
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*
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* ------------------------------------------------------------
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _NAND_DEFS_H_
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#define _NAND_DEFS_H_
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#include <asm/arch/hardware.h>
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#define MASK_CLE 0x10
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#define MASK_ALE 0x0a
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#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10))
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#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a))
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#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE)
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typedef struct {
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u_int32_t NRCSR;
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u_int32_t AWCCR;
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u_int8_t RSVD0[8];
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u_int32_t AB1CR;
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u_int32_t AB2CR;
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u_int32_t AB3CR;
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u_int32_t AB4CR;
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u_int8_t RSVD1[32];
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u_int32_t NIRR;
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u_int32_t NIMR;
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u_int32_t NIMSR;
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u_int32_t NIMCR;
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u_int8_t RSVD2[16];
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u_int32_t NANDFCR;
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u_int32_t NANDFSR;
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u_int8_t RSVD3[8];
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u_int32_t NANDF1ECC;
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u_int32_t NANDF2ECC;
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u_int32_t NANDF3ECC;
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u_int32_t NANDF4ECC;
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u_int8_t RSVD4[4];
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u_int32_t IODFTECR;
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u_int32_t IODFTGCR;
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u_int8_t RSVD5[4];
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u_int32_t IODFTMRLR;
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u_int32_t IODFTMRMR;
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u_int32_t IODFTMRMSBR;
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u_int8_t RSVD6[20];
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u_int32_t MODRNR;
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u_int8_t RSVD7[76];
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u_int32_t CE0DATA;
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u_int32_t CE0ALE;
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u_int32_t CE0CLE;
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u_int8_t RSVD8[4];
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u_int32_t CE1DATA;
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u_int32_t CE1ALE;
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u_int32_t CE1CLE;
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u_int8_t RSVD9[4];
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u_int32_t CE2DATA;
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u_int32_t CE2ALE;
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u_int32_t CE2CLE;
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u_int8_t RSVD10[4];
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u_int32_t CE3DATA;
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u_int32_t CE3ALE;
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u_int32_t CE3CLE;
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} nand_registers;
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typedef volatile nand_registers *nandregs;
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#define NAND_READ_START 0x00
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#define NAND_READ_END 0x30
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#define NAND_STATUS 0x70
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#ifdef CFG_NAND_HW_ECC
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#define NAND_Ecc_P1e (1 << 0)
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#define NAND_Ecc_P2e (1 << 1)
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#define NAND_Ecc_P4e (1 << 2)
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#define NAND_Ecc_P8e (1 << 3)
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#define NAND_Ecc_P16e (1 << 4)
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#define NAND_Ecc_P32e (1 << 5)
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#define NAND_Ecc_P64e (1 << 6)
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#define NAND_Ecc_P128e (1 << 7)
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#define NAND_Ecc_P256e (1 << 8)
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#define NAND_Ecc_P512e (1 << 9)
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#define NAND_Ecc_P1024e (1 << 10)
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#define NAND_Ecc_P2048e (1 << 11)
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#define NAND_Ecc_P1o (1 << 16)
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#define NAND_Ecc_P2o (1 << 17)
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#define NAND_Ecc_P4o (1 << 18)
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#define NAND_Ecc_P8o (1 << 19)
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#define NAND_Ecc_P16o (1 << 20)
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#define NAND_Ecc_P32o (1 << 21)
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#define NAND_Ecc_P64o (1 << 22)
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#define NAND_Ecc_P128o (1 << 23)
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#define NAND_Ecc_P256o (1 << 24)
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#define NAND_Ecc_P512o (1 << 25)
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#define NAND_Ecc_P1024o (1 << 26)
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#define NAND_Ecc_P2048o (1 << 27)
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#define TF(v) (v ? 1 : 0)
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#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
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#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
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#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
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#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
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#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
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#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
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#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
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#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
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#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
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#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
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#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
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#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
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#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
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#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
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#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
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#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
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#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
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#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
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#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
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#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
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#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
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#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
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#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
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#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
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#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
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#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
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#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
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#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
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#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
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#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
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#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
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#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
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#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
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#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
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#endif
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#endif
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