Your ROOT_URL in app.ini is https://src.whiteboxsystems.nl/ but you are visiting http://src.whiteboxsystems.nl/Whitebox/u-boot/blame/commit/4fcd0b33c7a0db2e86cccdc1831db235a6bc1b2d/board/amcc/luan/init.S You should set ROOT_URL correctly, otherwise the web may not work correctly.
Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
34451 Commits
3 Branches
0 Tags
148 MiB
u-boot/board/amcc/luan/init.S

60 lines
1.8 KiB
Raw Normal View History Unescape

Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. Patch by John Otken, 23 Nov 2005
20 years ago
/*
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
Coding Style cleanup: remove trailing white space Signed-off-by: Wolfgang Denk <wd@denx.de>
12 years ago
* SPDX-License-Identifier: GPL-2.0+
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
*/
Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. Patch by John Otken, 23 Nov 2005
20 years ago
#include <ppc_asm.tmpl>
#include <config.h>
Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>" The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years ago
#include <asm/mmu.h>
ppc4xx: Use common NS16550 driver for PPC4xx UART This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
#include <asm/ppc4xx.h>
Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. Patch by John Otken, 23 Nov 2005
20 years ago
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
.section .bootpg,"ax"
.globl tlbtab
Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. Patch by John Otken, 23 Nov 2005
20 years ago
tlbtab:
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
/* internal ram (l2 cache) */
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
/* peripherals at f0000000 */
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
/* PCI */
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
[PATCH] Update AMCC Luan 440SP eval board support The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
tlbtab_end