upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
64 lines
1.7 KiB
64 lines
1.7 KiB
12 years ago
|
/*
|
||
|
|
* Copyright (c) 2013 Xilinx Inc.
|
||
|
|
*
|
||
|
|
* See file CREDITS for list of people who contributed to this
|
||
|
|
* project.
|
||
|
|
*
|
||
|
|
* This program is free software; you can redistribute it and/or
|
||
|
|
* modify it under the terms of the GNU General Public License as
|
||
|
|
* published by the Free Software Foundation; either version 2 of
|
||
|
|
* the License, or (at your option) any later version.
|
||
|
|
*
|
||
|
|
* This program is distributed in the hope that it will be useful,
|
||
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||
|
|
* GNU General Public License for more details.
|
||
|
|
*
|
||
|
|
* You should have received a copy of the GNU General Public License
|
||
|
|
* along with this program; if not, write to the Free Software
|
||
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||
|
|
* MA 02111-1307 USA
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include <common.h>
|
||
|
|
#include <asm/io.h>
|
||
|
|
#include <malloc.h>
|
||
|
|
#include <asm/arch/hardware.h>
|
||
|
|
|
||
|
|
#define SLCR_LOCK_MAGIC 0x767B
|
||
|
|
#define SLCR_UNLOCK_MAGIC 0xDF0D
|
||
|
|
|
||
|
|
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
|
||
|
|
|
||
|
|
void zynq_slcr_lock(void)
|
||
|
|
{
|
||
|
|
if (!slcr_lock)
|
||
|
|
writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
|
||
|
|
}
|
||
|
|
|
||
|
|
void zynq_slcr_unlock(void)
|
||
|
|
{
|
||
|
|
if (slcr_lock)
|
||
|
|
writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Reset the entire system */
|
||
|
|
void zynq_slcr_cpu_reset(void)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Unlock the SLCR then reset the system.
|
||
|
|
* Note that this seems to require raw i/o
|
||
|
|
* functions or there's a lockup?
|
||
|
|
*/
|
||
|
|
zynq_slcr_unlock();
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Clear 0x0F000000 bits of reboot status register to workaround
|
||
|
|
* the FSBL not loading the bitstream after soft-reboot
|
||
|
|
* This is a temporary solution until we know more.
|
||
|
|
*/
|
||
|
|
clrbits_le32(&slcr_base->reboot_status, 0xF000000);
|
||
|
|
|
||
|
|
writel(1, &slcr_base->pss_rst_ctrl);
|
||
|
|
}
|