upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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151 lines
4.8 KiB
151 lines
4.8 KiB
10 years ago
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/*
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* Freescale DSPI Module Defines
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*
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* Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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* Chao Fu (B44548@freesacle.com)
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* Haikun Wang (B53464@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _FSL_DSPI_H_
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#define _FSL_DSPI_H_
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/* DMA Serial Peripheral Interface (DSPI) */
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struct dspi {
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u32 mcr; /* 0x00 */
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u32 resv0; /* 0x04 */
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u32 tcr; /* 0x08 */
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u32 ctar[8]; /* 0x0C - 0x28 */
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u32 sr; /* 0x2C */
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u32 irsr; /* 0x30 */
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u32 tfr; /* 0x34 - PUSHR */
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u32 rfr; /* 0x38 - POPR */
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#ifdef CONFIG_MCF547x_8x
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u32 tfdr[4]; /* 0x3C */
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u8 resv2[0x30]; /* 0x40 */
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u32 rfdr[4]; /* 0x7C */
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#else
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u32 tfdr[16]; /* 0x3C */
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u32 rfdr[16]; /* 0x7C */
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#endif
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};
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/* Module configuration */
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#define DSPI_MCR_MSTR 0x80000000
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#define DSPI_MCR_CSCK 0x40000000
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#define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28)
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#define DSPI_MCR_FRZ 0x08000000
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#define DSPI_MCR_MTFE 0x04000000
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#define DSPI_MCR_PCSSE 0x02000000
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#define DSPI_MCR_ROOE 0x01000000
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#define DSPI_MCR_PCSIS(x) (1 << (16 + (x)))
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#define DSPI_MCR_PCSIS_MASK (0xff << 16)
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#define DSPI_MCR_CSIS7 0x00800000
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#define DSPI_MCR_CSIS6 0x00400000
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#define DSPI_MCR_CSIS5 0x00200000
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#define DSPI_MCR_CSIS4 0x00100000
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#define DSPI_MCR_CSIS3 0x00080000
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#define DSPI_MCR_CSIS2 0x00040000
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#define DSPI_MCR_CSIS1 0x00020000
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#define DSPI_MCR_CSIS0 0x00010000
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#define DSPI_MCR_DOZE 0x00008000
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#define DSPI_MCR_MDIS 0x00004000
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#define DSPI_MCR_DTXF 0x00002000
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#define DSPI_MCR_DRXF 0x00001000
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#define DSPI_MCR_CTXF 0x00000800
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#define DSPI_MCR_CRXF 0x00000400
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#define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8)
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#define DSPI_MCR_FCPCS 0x00000001
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#define DSPI_MCR_PES 0x00000001
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#define DSPI_MCR_HALT 0x00000001
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/* Transfer count */
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#define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16)
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/* Clock and transfer attributes */
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#define DSPI_CTAR(x) (0x0c + (x * 4))
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#define DSPI_CTAR_DBR 0x80000000
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#define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27)
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#define DSPI_CTAR_CPOL 0x04000000
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#define DSPI_CTAR_CPHA 0x02000000
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#define DSPI_CTAR_LSBFE 0x01000000
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#define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22)
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#define DSPI_CTAR_PCSSCK_7CLK 0x00A00000
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#define DSPI_CTAR_PCSSCK_5CLK 0x00800000
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#define DSPI_CTAR_PCSSCK_3CLK 0x00400000
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#define DSPI_CTAR_PCSSCK_1CLK 0x00000000
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#define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20)
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#define DSPI_CTAR_PASC_7CLK 0x00300000
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#define DSPI_CTAR_PASC_5CLK 0x00200000
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#define DSPI_CTAR_PASC_3CLK 0x00100000
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#define DSPI_CTAR_PASC_1CLK 0x00000000
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#define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18)
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#define DSPI_CTAR_PDT_7CLK 0x000A0000
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#define DSPI_CTAR_PDT_5CLK 0x00080000
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#define DSPI_CTAR_PDT_3CLK 0x00040000
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#define DSPI_CTAR_PDT_1CLK 0x00000000
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#define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16)
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#define DSPI_CTAR_PBR_7CLK 0x00030000
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#define DSPI_CTAR_PBR_5CLK 0x00020000
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#define DSPI_CTAR_PBR_3CLK 0x00010000
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#define DSPI_CTAR_PBR_1CLK 0x00000000
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#define DSPI_CTAR_CSSCK(x) (((x) & 0x0F) << 12)
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#define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8)
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#define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4)
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#define DSPI_CTAR_BR(x) ((x) & 0x0F)
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/* Status */
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#define DSPI_SR_TCF 0x80000000
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#define DSPI_SR_TXRXS 0x40000000
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#define DSPI_SR_EOQF 0x10000000
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#define DSPI_SR_TFUF 0x08000000
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#define DSPI_SR_TFFF 0x02000000
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#define DSPI_SR_RFOF 0x00080000
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#define DSPI_SR_RFDF 0x00020000
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#define DSPI_SR_TXCTR(x) (((x) & 0x0000F000) >> 12)
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#define DSPI_SR_TXPTR(x) (((x) & 0x00000F00) >> 8)
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#define DSPI_SR_RXCTR(x) (((x) & 0x000000F0) >> 4)
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#define DSPI_SR_RXPTR(x) ((x) & 0x0000000F)
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/* DMA/interrupt request selct and enable */
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#define DSPI_IRSR_TCFE 0x80000000
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#define DSPI_IRSR_EOQFE 0x10000000
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#define DSPI_IRSR_TFUFE 0x08000000
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#define DSPI_IRSR_TFFFE 0x02000000
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#define DSPI_IRSR_TFFFS 0x01000000
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#define DSPI_IRSR_RFOFE 0x00080000
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#define DSPI_IRSR_RFDFE 0x00020000
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#define DSPI_IRSR_RFDFS 0x00010000
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/* Transfer control - 32-bit access */
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#define DSPI_TFR_PCS(x) (((1 << x) & 0x0000003f) << 16)
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#define DSPI_TFR_CONT 0x80000000
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#define DSPI_TFR_CTAS(x) (((x) & 0x07) << 28)
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#define DSPI_TFR_EOQ 0x08000000
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#define DSPI_TFR_CTCNT 0x04000000
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#define DSPI_TFR_CS7 0x00800000
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#define DSPI_TFR_CS6 0x00400000
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#define DSPI_TFR_CS5 0x00200000
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#define DSPI_TFR_CS4 0x00100000
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#define DSPI_TFR_CS3 0x00080000
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#define DSPI_TFR_CS2 0x00040000
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#define DSPI_TFR_CS1 0x00020000
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#define DSPI_TFR_CS0 0x00010000
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/* Transfer Fifo */
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#define DSPI_TFR_TXDATA(x) ((x) & 0x0000FFFF)
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/* Bit definitions and macros for DRFR */
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#define DSPI_RFR_RXDATA(x) ((x) & 0x0000FFFF)
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/* Bit definitions and macros for DTFDR group */
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#define DSPI_TFDR_TXDATA(x) ((x) & 0x0000FFFF)
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#define DSPI_TFDR_TXCMD(x) (((x) & 0x0000FFFF) << 16)
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/* Bit definitions and macros for DRFDR group */
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#define DSPI_RFDR_RXDATA(x) ((x) & 0x0000FFFF)
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#endif /* _FSL_DSPI_H_ */
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