upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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98 lines
3.6 KiB
98 lines
3.6 KiB
19 years ago
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/**
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* @file IxEthAccMii_p.h
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*
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* @author Intel Corporation
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* @date
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*
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* @brief MII Header file
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*
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* Design Notes:
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IxEthAccMii_p_H
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#define IxEthAccMii_p_H
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/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/
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#define IXP425_ETH_ACC_MII_MAX_REG 32 /* max register per phy */
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#define IX_ETH_ACC_MII_REG_SHL 16
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#define IX_ETH_ACC_MII_ADDR_SHL 21
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/* Definitions for MII access routines*/
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#define IX_ETH_ACC_MII_GO BIT(31)
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#define IX_ETH_ACC_MII_WRITE BIT(26)
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#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS 5
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#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS 100
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#define IX_ETH_ACC_MII_READ_FAIL BIT(31)
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#define IX_ETH_ACC_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */
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#define IX_ETH_ACC_MII_PHY_NO_DELAY 0x0 /* do not delay */
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#define IX_ETH_ACC_MII_PHY_NULL 0xff /* PHY is not present */
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#define IX_ETH_ACC_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */
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#ifndef IX_ETH_ACC_MII_MONITOR_DELAY
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# define IX_ETH_ACC_MII_MONITOR_DELAY 0x5 /* in seconds */
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#endif
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/* Register definition */
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#define IX_ETH_ACC_MII_CTRL_REG 0x0 /* Control Register */
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#define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */
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#define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
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#define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
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#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
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/* Advertisement Register */
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#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
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/* partner ability Register */
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#define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
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/* Expansion Register */
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#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
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/* next-page transmit Register */
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IxEthAccStatus ixEthAccMdioShow (void);
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IxEthAccStatus ixEthAccMiiInit(void);
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void ixEthAccMiiUnload(void);
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#endif /*IxEthAccMii_p_H*/
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