upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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69 lines
1.6 KiB
69 lines
1.6 KiB
16 years ago
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <ioports.h>
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#include <lmb.h>
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#include <asm/io.h>
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#include "mp.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if (CONFIG_NUM_CPUS > 1)
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void cpu_mp_lmb_reserve(struct lmb *lmb)
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{
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u32 bootpg;
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/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
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if ((u64)gd->ram_size > 0xfffff000)
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bootpg = 0xfff00000;
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else
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bootpg = gd->ram_size - (1024 * 1024);
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/* tell u-boot we stole a page */
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lmb_reserve(lmb, bootpg, 4096);
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}
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/*
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* Copy the code for other cpus to execute into an
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* aligned location accessible via BPTR
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*/
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void setup_mp(void)
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{
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extern ulong __secondary_start_page;
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ulong fixup = (ulong)&__secondary_start_page;
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u32 bootpg;
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u32 bootpg_va;
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/*
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* If we have 4G or more of memory, put the boot page at 4Gb-1M.
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* Otherwise, put it at the very end of RAM.
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*/
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if (gd->ram_size > 0xfffff000)
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bootpg = 0xfff00000;
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else
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bootpg = gd->ram_size - (1024 * 1024);
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if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
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/* We're not covered by the DDR mapping, set up BAT */
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write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
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BATU_VS | BATU_VP,
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bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
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bootpg_va = CONFIG_SYS_SCRATCH_VA;
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} else {
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bootpg_va = bootpg;
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}
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memcpy((void *)bootpg_va, (void *)fixup, 4096);
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flush_cache(bootpg_va, 4096);
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/* remove the temporary BAT mapping */
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if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
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write_bat(DBAT7, 0, 0);
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/* If the physical location of bootpg is not at fff00000, set BPTR */
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if (bootpg != 0xfff00000)
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out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
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(bootpg >> 12));
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}
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#endif
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