upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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78 lines
2.1 KiB
78 lines
2.1 KiB
21 years ago
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/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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* 2003-2004 (c) MontaVista Software, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "config.h"
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#include "version.h"
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20 years ago
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.globl lowlevel_init
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lowlevel_init:
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21 years ago
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/* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
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* However the darn thing leaves the MMU enabled before handing control
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20 years ago
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* over to us. So we need to disable the MMU and we use lowlevel_init
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21 years ago
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* to do it.
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*/
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@ The following code segment was borrowed with gratitude from:
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@ linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
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@ Data cache might be active.
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@ Be sure to flush kernel binary out of the cache,
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@ whatever state it is, before it is turned off.
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@ This is done by fetching through currently executed
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@ memory to be sure we hit the same cache.
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bic r2, pc, #0x1f
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add r3, r2, #0x4000 @ 16 kb is quite enough...
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1: ldr r0, [r2], #32
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teq r2, r3
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bne 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
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@ disabling MMU and caches
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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bic r0, r0, #0x0d @ clear WB, DC, MMU
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bic r0, r0, #0x1000 @ clear Icache
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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nop
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nop
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b 2f
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2:
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nop
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nop
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nop
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nop
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nop
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mov pc, lr
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