upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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111 lines
4.3 KiB
111 lines
4.3 KiB
21 years ago
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/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* FILENAME:
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*
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* xdma_channel_i.h
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*
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* DESCRIPTION:
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*
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* This file contains data which is shared internal data for the DMA channel
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* component. It is also shared with the buffer descriptor component which is
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* very tightly coupled with the DMA channel component.
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*
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* NOTES:
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*
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* The last buffer descriptor constants must be located here to prevent a
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* circular dependency between the DMA channel component and the buffer
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* descriptor component.
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*
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******************************************************************************/
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#ifndef XDMA_CHANNEL_I_H /* prevent circular inclusions */
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#define XDMA_CHANNEL_I_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#include "xbasic_types.h"
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#include "xstatus.h"
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#include "xversion.h"
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/************************** Constant Definitions *****************************/
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#define XDC_DMA_CHANNEL_V1_00_A "1.00a"
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/* the following constant provides access to the bit fields of the DMA control
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* register (DMACR) which must be shared between the DMA channel component
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* and the buffer descriptor component
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*/
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#define XDC_CONTROL_LAST_BD_MASK 0x02000000UL /* last buffer descriptor */
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/* the following constant provides access to the bit fields of the DMA status
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* register (DMASR) which must be shared between the DMA channel component
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* and the buffer descriptor component
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*/
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#define XDC_STATUS_LAST_BD_MASK 0x10000000UL /* last buffer descriptor */
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/* the following constants provide access to each of the registers of a DMA
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* channel
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*/
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#define XDC_RST_REG_OFFSET 0 /* reset register */
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#define XDC_MI_REG_OFFSET 0 /* module information register */
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#define XDC_DMAC_REG_OFFSET 4 /* DMA control register */
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#define XDC_SA_REG_OFFSET 8 /* source address register */
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#define XDC_DA_REG_OFFSET 12 /* destination address register */
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#define XDC_LEN_REG_OFFSET 16 /* length register */
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#define XDC_DMAS_REG_OFFSET 20 /* DMA status register */
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#define XDC_BDA_REG_OFFSET 24 /* buffer descriptor address register */
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#define XDC_SWCR_REG_OFFSET 28 /* software control register */
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#define XDC_UPC_REG_OFFSET 32 /* unserviced packet count register */
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#define XDC_PCT_REG_OFFSET 36 /* packet count threshold register */
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#define XDC_PWB_REG_OFFSET 40 /* packet wait bound register */
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#define XDC_IS_REG_OFFSET 44 /* interrupt status register */
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#define XDC_IE_REG_OFFSET 48 /* interrupt enable register */
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/* the following constant is written to the reset register to reset the
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* DMA channel
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*/
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#define XDC_RESET_MASK 0x0000000AUL
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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#endif /* end of protection macro */
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