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/*
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* Configuration for Xilinx ZynqMP zcu102
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*
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* (C) Copyright 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_ZYNQMP_ZCU102_H
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#define __CONFIG_ZYNQMP_ZCU102_H
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#define CONFIG_ZYNQ_SDHCI1
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#define CONFIG_ZYNQ_I2C0
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#define CONFIG_ZYNQ_I2C1
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#define CONFIG_SYS_I2C_MAX_HOPS 1
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#define CONFIG_SYS_NUM_I2C_BUSES 18
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#define CONFIG_SYS_I2C_BUSES { \
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{0, {I2C_NULL_HOP} }, \
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{0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
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{0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
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{0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
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{1, {I2C_NULL_HOP} }, \
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{1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
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{1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
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{1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
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{1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
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{1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
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{1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
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}
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#define CONFIG_SYS_I2C_ZYNQ
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#define CONFIG_PCA953X
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#define CONFIG_CMD_PCA953X
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#define CONFIG_CMD_PCA953X_INFO
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#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_ZYNQ_EEPROM_BUS 5
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#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
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#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
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#include <configs/xilinx_zynqmp.h>
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#endif /* __CONFIG_ZYNQMP_ZCU102_H */
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