upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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75 lines
2.2 KiB
75 lines
2.2 KiB
11 years ago
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2013 SolidRun ltd.
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* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* ZQ Calibrations */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
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/* write leveling */
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
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/*
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* DQS gating, read delay, write delay calibration values
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* based on calibration compare of 0x00ffff00
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*/
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
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/* read data bit delay */
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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/* Complete calibration by forced measurement */
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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/*
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* MMDC init:
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* in DDR3, 32-bit mode, only MMDC0 is initiated:
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*/
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
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DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
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/* CS0_END - 0x2fffffff, 512M */
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
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/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
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DATA 4, 0x021b0400, 0x11420000
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/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
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DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
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/*
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* Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
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* MR2
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*/
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
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/* MR3 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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/* MR1 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
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/* MR0 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
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/* ZQ calibration */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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/* final DDR setup */
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DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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