upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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28 lines
945 B
28 lines
945 B
23 years ago
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#ifndef __BOARD_CPU86__
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#define __BOARD_CPU86__
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#include <config.h>
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#define REG8(x) (*(volatile unsigned char *)(x))
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/* CPU86 register definitions */
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#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00)
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#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01)
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#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02)
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#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03)
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#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04)
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#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05)
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#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04)
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#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07)
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#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80)
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#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81)
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#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82)
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#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83)
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#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84)
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/* Board Control Register bits */
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#define CPU86_BCR_FWPT 0x01
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#define CPU86_BCR_FWRE 0x02
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#endif /* __BOARD_CPU86__ */
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