upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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412 lines
10 KiB
412 lines
10 KiB
8 years ago
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/*
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* DTS File for HiSilicon Hi3798cv200 SoC.
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*
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*
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* Released under the GPLv2 only.
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <dt-bindings/clock/histb-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/ti-syscon.h>
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/ {
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compatible = "hisilicon,hi3798cv200";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
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<0x0 0xf1002000 0x0 0x100>; /* GICC */
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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soc: soc@f0000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xf0000000 0x10000000>;
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crg: clock-reset-controller@8a22000 {
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compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
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reg = <0x8a22000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <2>;
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gmacphyrst: reset-controller {
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compatible = "ti,syscon-reset";
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#reset-cells = <1>;
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ti,reset-bits =
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<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
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DEASSERT_SET|STATUS_NONE)>,
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<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
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DEASSERT_SET|STATUS_NONE)>;
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};
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};
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sysctrl: system-controller@8000000 {
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compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
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reg = <0x8000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <2>;
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};
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uart0: serial@8b00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x8b00000 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysctrl HISTB_UART0_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart2: serial@8b02000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x8b02000 0x1000>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_UART2_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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i2c0: i2c@8b10000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b10000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C0_CLK>;
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status = "disabled";
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};
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i2c1: i2c@8b11000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b11000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C1_CLK>;
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status = "disabled";
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};
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i2c2: i2c@8b12000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b12000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C2_CLK>;
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status = "disabled";
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};
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i2c3: i2c@8b13000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b13000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C3_CLK>;
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status = "disabled";
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};
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i2c4: i2c@8b14000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b14000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C4_CLK>;
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status = "disabled";
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};
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spi0: spi@8b1a000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x8b1a000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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cs-gpios = <&gpio7 1 0>;
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clocks = <&crg HISTB_SPI0_CLK>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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emmc: mmc@9830000 {
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compatible = "snps,dw-mshc";
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reg = <0x9830000 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_MMC_CIU_CLK>,
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<&crg HISTB_MMC_BIU_CLK>;
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clock-names = "ciu", "biu";
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};
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gpio0: gpio@8b20000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b20000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio1: gpio@8b21000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b21000 0x1000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio2: gpio@8b22000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b22000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio3: gpio@8b23000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b23000 0x1000>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio4: gpio@8b24000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b24000 0x1000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio5: gpio@8004000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8004000 0x1000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio6: gpio@8b26000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b26000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio7: gpio@8b27000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b27000 0x1000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio8: gpio@8b28000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b28000 0x1000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio9: gpio@8b29000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b29000 0x1000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio10: gpio@8b2a000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b2a000 0x1000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio11: gpio@8b2b000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b2b000 0x1000>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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|
|
clock-names = "apb_pclk";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpio12: gpio@8b2c000 {
|
||
|
|
compatible = "arm,pl061", "arm,primecell";
|
||
|
|
reg = <0x8b2c000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
clocks = <&crg HISTB_APB_CLK>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gmac0: ethernet@9840000 {
|
||
|
|
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
|
||
|
|
reg = <0x9840000 0x1000>,
|
||
|
|
<0x984300c 0x4>;
|
||
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&crg HISTB_ETH0_MAC_CLK>,
|
||
|
|
<&crg HISTB_ETH0_MACIF_CLK>;
|
||
|
|
clock-names = "mac_core", "mac_ifc";
|
||
|
|
resets = <&crg 0xcc 8>,
|
||
|
|
<&crg 0xcc 10>,
|
||
|
|
<&gmacphyrst 0>;
|
||
|
|
reset-names = "mac_core", "mac_ifc", "phy";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gmac1: ethernet@9841000 {
|
||
|
|
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
|
||
|
|
reg = <0x9841000 0x1000>,
|
||
|
|
<0x9843010 0x4>;
|
||
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&crg HISTB_ETH1_MAC_CLK>,
|
||
|
|
<&crg HISTB_ETH1_MACIF_CLK>;
|
||
|
|
clock-names = "mac_core", "mac_ifc";
|
||
|
|
resets = <&crg 0xcc 9>,
|
||
|
|
<&crg 0xcc 11>,
|
||
|
|
<&gmacphyrst 1>;
|
||
|
|
reset-names = "mac_core", "mac_ifc", "phy";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ir: ir@8001000 {
|
||
|
|
compatible = "hisilicon,hix5hd2-ir";
|
||
|
|
reg = <0x8001000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&sysctrl HISTB_IR_CLK>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|