upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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99 lines
2.9 KiB
99 lines
2.9 KiB
24 years ago
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#ifndef __dimm_h
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#define __dimm_h
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/*
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* Module name: %M%
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* Description:
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* Serial Presence Detect Definitions Module
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* SCCS identification: %I%
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* Branch: %B%
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* Sequence: %S%
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* Date newest applied delta was created (MM/DD/YY): %G%
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* Time newest applied delta was created (HH:MM:SS): %U%
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* SCCS file name %F%
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* Fully qualified SCCS file name:
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* %P%
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* Copyright:
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* (C) COPYRIGHT MOTOROLA, INC. 1996
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* ALL RIGHTS RESERVED
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* Notes:
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* 1. All data was taken from an IBM application note titled
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* "Serial Presence Detect Definitions".
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* History:
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* Date Who
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*
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* 10/24/96 Rob Baxter
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* Initial release.
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*
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*/
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/*
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* serial PD byte assignment address map (256 byte EEPROM)
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*/
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typedef struct dimm
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{
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uchar n_bytes; /* 00 number of bytes written/used */
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uchar t_bytes; /* 01 total number of bytes in serial PD device */
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uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */
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uchar n_row; /* 03 number of rows */
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uchar n_col; /* 04 number of columns */
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uchar n_banks; /* 05 number of banks */
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uchar data_w_lo; /* 06 data width */
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uchar data_w_hi; /* 07 data width */
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uchar ifl; /* 08 interface levels */
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uchar a_ras; /* 09 RAS access */
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uchar a_cas; /* 0A CAS access */
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uchar ct; /* 0B configuration type (non-parity/parity/ECC) */
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uchar refresh_rt; /* 0C refresh rate/type */
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uchar p_dram_o; /* 0D primary DRAM organization */
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uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */
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uchar reserved[17]; /* 0F reserved fields for future offerings */
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uchar ss_info[32]; /* 20 superset information (may be used in the future) */
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uchar m_info[64]; /* 40 manufacturer information (optional) */
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uchar unused[128]; /* 80 unused storage locations */
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} dimm_t;
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/*
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* memory type definitions
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*/
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#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */
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#define DIMM_MT_EDO 2 /* EDO (extended data out) */
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#define DIMM_MT_PN 3 /* pipelined nibble */
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#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */
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/*
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* row addresses definitions
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*/
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#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */
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#define DIMM_RA_MASK 0x7f /* number of row addresses mask */
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/*
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* module interface levels definitions
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*/
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#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */
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#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */
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#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */
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#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */
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#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */
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/*
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* DIMM configuration type definitions
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*/
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#define DIMM_CT_NONE 0 /* none */
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#define DIMM_CT_PARITY 1 /* parity */
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#define DIMM_CT_ECC 2 /* ECC */
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/*
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* row addresses definitions
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*/
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#define DIMM_RRT_SR (1<<7) /* self refresh flag */
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#define DIMM_RRT_MASK 0x7f /* refresh rate mask */
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#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */
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#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */
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#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */
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#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */
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#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */
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#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */
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#endif /* __dimm_h */
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