upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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98 lines
3.5 KiB
98 lines
3.5 KiB
17 years ago
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/* psr.h: This file holds the macros for masking off various parts of
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* the processor status register on the Sparc. This is valid
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* for Version 8. On the V9 this is renamed to the PSTATE
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* register and its members are accessed as fields like
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* PSTATE.PRIV for the current CPU privilege level.
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*
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* taken from the SPARC port of Linux,
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*
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* Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __SPARC_PSR_H__
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#define __SPARC_PSR_H__
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/* The Sparc PSR fields are laid out as the following:
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*
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* ------------------------------------------------------------------------
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* | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
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* | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
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* ------------------------------------------------------------------------
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*/
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#define PSR_CWP 0x0000001f /* current window pointer */
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#define PSR_ET 0x00000020 /* enable traps field */
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#define PSR_PS 0x00000040 /* previous privilege level */
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#define PSR_S 0x00000080 /* current privilege level */
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#define PSR_PIL 0x00000f00 /* processor interrupt level */
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#define PSR_EF 0x00001000 /* enable floating point */
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#define PSR_EC 0x00002000 /* enable co-processor */
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#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
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#define PSR_ICC 0x00f00000 /* integer condition codes */
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#define PSR_C 0x00100000 /* carry bit */
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#define PSR_V 0x00200000 /* overflow bit */
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#define PSR_Z 0x00400000 /* zero bit */
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#define PSR_N 0x00800000 /* negative bit */
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#define PSR_VERS 0x0f000000 /* cpu-version field */
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#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
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#define PSR_PIL_OFS 8
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#ifndef __ASSEMBLY__
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/* Get the %psr register. */
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extern __inline__ unsigned int get_psr(void)
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{
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unsigned int psr;
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__asm__ __volatile__("rd %%psr, %0\n\t"
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"nop\n\t" "nop\n\t" "nop\n\t":"=r"(psr)
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: /* no inputs */
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:"memory");
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return psr;
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}
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extern __inline__ void put_psr(unsigned int new_psr)
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{
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__asm__ __volatile__("wr %0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t": /* no outputs */
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:"r"(new_psr)
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:"memory", "cc");
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}
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/* Get the %fsr register. Be careful, make sure the floating point
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* enable bit is set in the %psr when you execute this or you will
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* incur a trap.
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*/
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extern unsigned int fsr_storage;
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extern __inline__ unsigned int get_fsr(void)
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{
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unsigned int fsr = 0;
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__asm__ __volatile__("st %%fsr, %1\n\t"
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"ld %1, %0\n\t":"=r"(fsr)
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:"m"(fsr_storage));
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return fsr;
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__SPARC_PSR_H__) */
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