upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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117 lines
3.5 KiB
117 lines
3.5 KiB
22 years ago
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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long int initdram (int board_type)
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{
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#ifndef CFG_RAMBOOT
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/* configure SDRAM start/end */
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#if defined(CONFIG_MPC5200)
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x00000018;/* 32M at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x02000000;/* disabled */
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004;
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000;
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#elif defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
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*(vu_long *)MPC5XXX_SDRAM_STOP = 0x000007ff;/* 64M */
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
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/* address select register */
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*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0000;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0004;
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x514f0000;
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#endif
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#else
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#ifdef CONFIG_MGT5100
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
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#endif
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#endif
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/* return total ram size */
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#if defined(CONFIG_MGT5100)
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return (64 * 1024 * 1024);
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#elif defined(CONFIG_MPC5200)
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return (32 * 1024 * 1024);
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#endif
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}
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int checkboard (void)
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{
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#if defined(CONFIG_MPC5200)
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puts ("Board: Motorola MPC5200 (IceCube)\n");
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#elif defined(CONFIG_MGT5100)
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puts ("Board: Motorola MGT5100 (IceCube)\n");
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#endif
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return 0;
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}
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void flash_preinit(void)
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{
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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#if defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
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#endif
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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