upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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386 lines
16 KiB
386 lines
16 KiB
11 years ago
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/*
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* (C) Copyright 2013
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* Avionic Design GmbH <www.avionic-design.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
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#define _PINMUX_CONFIG_TAMONTEN_NG_H_
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#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_DEFAULT, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_##_od, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
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}
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#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
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{ \
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.padgrp = PDRIVE_PINGROUP_##_padgrp, \
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.slwf = _slwf, \
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.slwr = _slwr, \
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.drvup = _drvup, \
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.drvdn = _drvdn, \
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.lpmd = PGRP_LPMD_##_lpmd, \
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.schmt = PGRP_SCHMT_##_schmt, \
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.hsm = PGRP_HSM_##_hsm, \
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}
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static struct pingroup_config tamonten_ng_pinmux_common[] = {
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/* SDMMC1 pinmux */
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DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
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/* SDMMC3 pinmux */
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DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_CS6_N, RSVD1, UP, NORMAL, INPUT),
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/* SDMMC4 pinmux */
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LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
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/* I2C1 pinmux */
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I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C2 pinmux */
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I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C3 pinmux */
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I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C4 pinmux */
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I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* Power I2C pinmux */
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I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* UART1 */
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DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
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/* UART2 */
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DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
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/* UART3 */
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DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
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/* UART4 */
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DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DIR, UARTD, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
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/* DAP */
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DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
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/* I2S1 */
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DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
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/* SPDIF */
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DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
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/* I2S2 */
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DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
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/* DAP4 */
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DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
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/* Tamonten GPIO */
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DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
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/* LCD */
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DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
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/* BT656 */
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LV_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(VI_D11, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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/* GPIOs */
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DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
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/* LCD BL */
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DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
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/* SPI4 */
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DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
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/* Video input GPIO */
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DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
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/* Sensor GPIO */
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DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* JTAG */
|
||
|
|
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
|
||
|
|
|
||
|
|
/* Power controls */
|
||
|
|
DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* SPI1 */
|
||
|
|
DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* PMU */
|
||
|
|
DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* PCI */
|
||
|
|
DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* HDMI */
|
||
|
|
DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct pingroup_config unused_pins_lowpower[] = {
|
||
|
|
/* UART1 - NC */
|
||
|
|
DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* UART2 - NC */
|
||
|
|
DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* DAP - NC */
|
||
|
|
DEFAULT_PINMUX(CLK1_REQ, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* DAP4 - NC */
|
||
|
|
DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* Tamonten GPIO - NC */
|
||
|
|
DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* BT656 - NC */
|
||
|
|
LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||
|
|
LV_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||
|
|
LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||
|
|
|
||
|
|
/* GPIO - NC */
|
||
|
|
DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* Video input - NC */
|
||
|
|
DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW11, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* KBC keys - NC */
|
||
|
|
DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* PMU - NC */
|
||
|
|
DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* Power rails GPIO - NC */
|
||
|
|
DEFAULT_PINMUX(SPI2_SCK, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
|
||
|
|
/* Others - NC */
|
||
|
|
DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct padctrl_config tamonten_ng_padctrl[] = {
|
||
|
|
/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||
|
|
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
|
||
|
|
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
|
||
|
|
};
|
||
|
|
#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */
|