upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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187 lines
7.1 KiB
187 lines
7.1 KiB
11 years ago
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/*
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* pinmux setup for siemens pxm2 board
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*
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* (C) Copyright 2013 Siemens Schweiz AG
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* u-boot:/board/ti/am335x/mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
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{-1},
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};
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#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */
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{OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */
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{-1},
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};
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#endif
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux i2c1_pin_mux[] = {
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{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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#ifndef CONFIG_NO_ETH
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static struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
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{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
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{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
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{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
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{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
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{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux rgmii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
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{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
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{OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
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{OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
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{OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
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{OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
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{OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */
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{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
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{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
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{OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */
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{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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#endif
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
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{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */
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{-1},
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};
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#endif
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static struct module_pin_mux lcdc_pin_mux[] = {
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{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */
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{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */
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{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */
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{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */
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{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */
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{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */
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{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */
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{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */
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{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */
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{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */
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{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */
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{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */
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{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */
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{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */
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{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */
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{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */
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{OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */
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{OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */
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{OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */
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{OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */
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{OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */
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{OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */
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{OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */
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{OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */
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{OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */
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{OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */
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{OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */
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{OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */
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{-1},
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};
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static struct module_pin_mux ecap0_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), (MODE(0))},
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{-1},
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};
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static struct module_pin_mux gpio_pin_mux[] = {
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{OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/
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{OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */
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{OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */
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{-1},
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};
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void enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_board_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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configure_module_pin_mux(i2c1_pin_mux);
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#ifdef CONFIG_NAND
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configure_module_pin_mux(nand_pin_mux);
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#endif
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#ifndef CONFIG_NO_ETH
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configure_module_pin_mux(rgmii1_pin_mux);
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configure_module_pin_mux(rgmii2_pin_mux);
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#endif
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#ifdef CONFIG_MMC
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configure_module_pin_mux(mmc0_pin_mux);
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#endif
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configure_module_pin_mux(lcdc_pin_mux);
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configure_module_pin_mux(gpio_pin_mux);
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configure_module_pin_mux(ecap0_pin_mux);
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}
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