upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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54 lines
1.8 KiB
54 lines
1.8 KiB
11 years ago
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SOCFPGA Documentation for U-Boot and SPL
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This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
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based SOCFPGA. To know more about the hardware itself, please refer to
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www.altera.com.
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--------------------------------------------
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socfpga_dw_mmc
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--------------------------------------------
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Here are macro and detailed configuration required to enable DesignWare SDMMC
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controller support within SOCFPGA
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#define CONFIG_MMC
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-> To enable the SD MMC framework support
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#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS)
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-> The base address of CSR register for DesignWare SDMMC controller
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#define CONFIG_GENERIC_MMC
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-> Enable the generic MMC driver
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
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-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
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#define CONFIG_DWMMC
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-> Enable the common DesignWare SDMMC controller framework
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#define CONFIG_SOCFPGA_DWMMC
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-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
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#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
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-> The FIFO depth for SOCFPGA DesignWare SDMMC controller
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#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
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-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
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the card to meet hold time requirements. SD clock is running at 50MHz and
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drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
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is 135 / 360 * 20ns = 7.5ns.
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#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
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-> Phase-shifted clock of sdmmc_clk used to sample the command and data from
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the card
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#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
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-> Bus width of data line which either 1, 4 or 8 and based on board routing.
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#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000
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-> The clock rate to controller. Do note the controller have a wrapper which
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divide the clock from PLL by 4.
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