upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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56 lines
2.0 KiB
56 lines
2.0 KiB
17 years ago
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/*
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* File: include/asm-blackfin/mach-bf527/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2007 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
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#define ANOMALY_05000301 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (1)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (1)
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/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
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#define ANOMALY_05000342 (1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000261 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#endif
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