upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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201 lines
5.1 KiB
201 lines
5.1 KiB
13 years ago
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/*
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* Copyright (c) 2012
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*
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* Gabriel Huau <contact@huau-gabriel.fr>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _S3C24X0_IOMUX_H_
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#define _S3C24X0_IOMUX_H_
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enum s3c2440_iomux_func {
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/* PORT A */
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IOMUXA_ADDR0 = 1,
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IOMUXA_ADDR16 = (1 << 1),
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IOMUXA_ADDR17 = (1 << 2),
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IOMUXA_ADDR18 = (1 << 3),
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IOMUXA_ADDR19 = (1 << 4),
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IOMUXA_ADDR20 = (1 << 5),
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IOMUXA_ADDR21 = (1 << 6),
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IOMUXA_ADDR22 = (1 << 7),
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IOMUXA_ADDR23 = (1 << 8),
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IOMUXA_ADDR24 = (1 << 9),
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IOMUXA_ADDR25 = (1 << 10),
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IOMUXA_ADDR26 = (1 << 11),
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IOMUXA_nGCS1 = (1 << 12),
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IOMUXA_nGCS2 = (1 << 13),
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IOMUXA_nGCS3 = (1 << 14),
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IOMUXA_nGCS4 = (1 << 15),
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IOMUXA_nGCS5 = (1 << 16),
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IOMUXA_CLE = (1 << 17),
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IOMUXA_ALE = (1 << 18),
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IOMUXA_nFWE = (1 << 19),
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IOMUXA_nFRE = (1 << 20),
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IOMUXA_nRSTOUT = (1 << 21),
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IOMUXA_nFCE = (1 << 22),
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/* PORT B */
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IOMUXB_nXDREQ0 = (2 << 20),
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IOMUXB_nXDACK0 = (2 << 18),
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IOMUXB_nXDREQ1 = (2 << 16),
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IOMUXB_nXDACK1 = (2 << 14),
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IOMUXB_nXBREQ = (2 << 12),
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IOMUXB_nXBACK = (2 << 10),
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IOMUXB_TCLK0 = (2 << 8),
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IOMUXB_TOUT3 = (2 << 6),
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IOMUXB_TOUT2 = (2 << 4),
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IOMUXB_TOUT1 = (2 << 2),
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IOMUXB_TOUT0 = 2,
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/* PORT C */
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IOMUXC_VS7 = (2 << 30),
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IOMUXC_VS6 = (2 << 28),
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IOMUXC_VS5 = (2 << 26),
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IOMUXC_VS4 = (2 << 24),
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IOMUXC_VS3 = (2 << 22),
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IOMUXC_VS2 = (2 << 20),
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IOMUXC_VS1 = (2 << 18),
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IOMUXC_VS0 = (2 << 16),
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IOMUXC_LCD_LPCREVB = (2 << 14),
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IOMUXC_LCD_LPCREV = (2 << 12),
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IOMUXC_LCD_LPCOE = (2 << 10),
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IOMUXC_VM = (2 << 8),
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IOMUXC_VFRAME = (2 << 6),
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IOMUXC_VLINE = (2 << 4),
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IOMUXC_VCLK = (2 << 2),
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IOMUXC_LEND = 2,
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IOMUXC_I2SSDI = (3 << 8),
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/* PORT D */
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IOMUXD_VS23 = (2 << 30),
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IOMUXD_VS22 = (2 << 28),
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IOMUXD_VS21 = (2 << 26),
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IOMUXD_VS20 = (2 << 24),
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IOMUXD_VS19 = (2 << 22),
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IOMUXD_VS18 = (2 << 20),
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IOMUXD_VS17 = (2 << 18),
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IOMUXD_VS16 = (2 << 16),
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IOMUXD_VS15 = (2 << 14),
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IOMUXD_VS14 = (2 << 12),
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IOMUXD_VS13 = (2 << 10),
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IOMUXD_VS12 = (2 << 8),
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IOMUXD_VS11 = (2 << 6),
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IOMUXD_VS10 = (2 << 4),
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IOMUXD_VS9 = (2 << 2),
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IOMUXD_VS8 = 2,
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IOMUXD_nSS0 = (3 << 30),
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IOMUXD_nSS1 = (3 << 28),
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IOMUXD_SPICLK1 = (3 << 20),
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IOMUXD_SPIMOSI1 = (3 << 18),
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IOMUXD_SPIMISO1 = (3 << 16),
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/* PORT E */
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IOMUXE_IICSDA = (2 << 30),
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IOMUXE_IICSCL = (2 << 28),
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IOMUXE_SPICLK0 = (2 << 26),
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IOMUXE_SPIMOSI0 = (2 << 24),
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IOMUXE_SPIMISO0 = (2 << 22),
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IOMUXE_SDDAT3 = (2 << 20),
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IOMUXE_SDDAT2 = (2 << 18),
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IOMUXE_SDDAT1 = (2 << 16),
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IOMUXE_SDDAT0 = (2 << 14),
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IOMUXE_SDCMD = (2 << 12),
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IOMUXE_SDCLK = (2 << 10),
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IOMUXE_I2SDO = (2 << 8),
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IOMUXE_I2SDI = (2 << 6),
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IOMUXE_CDCLK = (2 << 4),
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IOMUXE_I2SSCLK = (2 << 2),
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IOMUXE_I2SLRCK = 2,
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IOMUXE_AC_SDATA_OUT = (3 << 8),
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IOMUXE_AC_SDATA_IN = (3 << 6),
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IOMUXE_AC_nRESET = (3 << 4),
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IOMUXE_AC_BIT_CLK = (3 << 2),
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IOMUXE_AC_SYNC = 3,
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/* PORT F */
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IOMUXF_EINT7 = (2 << 14),
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IOMUXF_EINT6 = (2 << 12),
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IOMUXF_EINT5 = (2 << 10),
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IOMUXF_EINT4 = (2 << 8),
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IOMUXF_EINT3 = (2 << 6),
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IOMUXF_EINT2 = (2 << 4),
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IOMUXF_EINT1 = (2 << 2),
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IOMUXF_EINT0 = 2,
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/* PORT G */
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IOMUXG_EINT23 = (2 << 30),
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IOMUXG_EINT22 = (2 << 28),
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IOMUXG_EINT21 = (2 << 26),
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IOMUXG_EINT20 = (2 << 24),
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IOMUXG_EINT19 = (2 << 22),
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IOMUXG_EINT18 = (2 << 20),
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IOMUXG_EINT17 = (2 << 18),
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IOMUXG_EINT16 = (2 << 16),
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IOMUXG_EINT15 = (2 << 14),
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IOMUXG_EINT14 = (2 << 12),
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IOMUXG_EINT13 = (2 << 10),
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IOMUXG_EINT12 = (2 << 8),
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IOMUXG_EINT11 = (2 << 6),
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IOMUXG_EINT10 = (2 << 4),
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IOMUXG_EINT9 = (2 << 2),
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IOMUXG_EINT8 = 2,
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IOMUXG_TCLK1 = (3 << 22),
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IOMUXG_nCTS1 = (3 << 20),
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IOMUXG_nRTS1 = (3 << 18),
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IOMUXG_SPICLK1 = (3 << 14),
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IOMUXG_SPIMOSI1 = (3 << 12),
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IOMUXG_SPIMISO1 = (3 << 10),
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IOMUXG_LCD_PWRDN = (3 << 8),
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IOMUXG_nSS1 = (3 << 6),
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IOMUXG_nSS0 = (3 << 4),
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/* PORT H */
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IOMUXH_CLKOUT1 = (2 << 20),
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IOMUXH_CLKOUT0 = (2 << 18),
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IOMUXH_UEXTCLK = (2 << 16),
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IOMUXH_RXD2 = (2 << 14),
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IOMUXH_TXD2 = (2 << 12),
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IOMUXH_RXD1 = (2 << 10),
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IOMUXH_TXD1 = (2 << 8),
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IOMUXH_RXD0 = (2 << 6),
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IOMUXH_TXD0 = (2 << 4),
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IOMUXH_nRTS0 = (2 << 2),
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IOMUXH_nCTS0 = 2,
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IOMUXH_nCTS1 = (3 << 14),
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IOMUXH_nRTS1 = (3 << 12),
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/* PORT J */
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IOMUXJ_CAMRESET = (2 << 24),
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IOMUXJ_CAMCLKOUT = (2 << 22),
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IOMUXJ_CAMHREF = (2 << 20),
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IOMUXJ_CAMVSYNC = (2 << 18),
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IOMUXJ_CAMPCLK = (2 << 16),
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IOMUXJ_CAMDATA7 = (2 << 14),
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IOMUXJ_CAMDATA6 = (2 << 12),
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IOMUXJ_CAMDATA5 = (2 << 10),
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IOMUXJ_CAMDATA4 = (2 << 8),
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IOMUXJ_CAMDATA3 = (2 << 6),
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IOMUXJ_CAMDATA2 = (2 << 4),
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IOMUXJ_CAMDATA1 = (2 << 2),
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IOMUXJ_CAMDATA0 = 2
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};
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#endif
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