upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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147 lines
4.5 KiB
147 lines
4.5 KiB
15 years ago
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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* Power Management Unit
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*/
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#ifndef __FTPMU010_H
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#define __FTPMU010_H
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struct ftpmu010 {
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unsigned int IDNMBR0; /* 0x00 */
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unsigned int reserved0; /* 0x04 */
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unsigned int OSCC; /* 0x08 */
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unsigned int PMODE; /* 0x0C */
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unsigned int PMCR; /* 0x10 */
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unsigned int PED; /* 0x14 */
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unsigned int PEDSR; /* 0x18 */
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unsigned int reserved1; /* 0x1C */
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unsigned int PMSR; /* 0x20 */
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unsigned int PGSR; /* 0x24 */
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unsigned int MFPSR; /* 0x28 */
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unsigned int MISC; /* 0x2C */
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unsigned int PDLLCR0; /* 0x30 */
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unsigned int PDLLCR1; /* 0x34 */
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unsigned int AHBMCLKOFF; /* 0x38 */
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unsigned int APBMCLKOFF; /* 0x3C */
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unsigned int DCSRCR0; /* 0x40 */
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unsigned int DCSRCR1; /* 0x44 */
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unsigned int DCSRCR2; /* 0x48 */
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unsigned int SDRAMHTC; /* 0x4C */
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unsigned int PSPR0; /* 0x50 */
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unsigned int PSPR1; /* 0x54 */
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unsigned int PSPR2; /* 0x58 */
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unsigned int PSPR3; /* 0x5C */
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unsigned int PSPR4; /* 0x60 */
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unsigned int PSPR5; /* 0x64 */
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unsigned int PSPR6; /* 0x68 */
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unsigned int PSPR7; /* 0x6C */
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unsigned int PSPR8; /* 0x70 */
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unsigned int PSPR9; /* 0x74 */
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unsigned int PSPR10; /* 0x78 */
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unsigned int PSPR11; /* 0x7C */
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unsigned int PSPR12; /* 0x80 */
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unsigned int PSPR13; /* 0x84 */
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unsigned int PSPR14; /* 0x88 */
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unsigned int PSPR15; /* 0x8C */
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unsigned int AHBDMA_RACCS; /* 0x90 */
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unsigned int reserved2; /* 0x94 */
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unsigned int reserved3; /* 0x98 */
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unsigned int JSS; /* 0x9C */
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unsigned int CFC_RACC; /* 0xA0 */
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unsigned int SSP1_RACC; /* 0xA4 */
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unsigned int UART1TX_RACC; /* 0xA8 */
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unsigned int UART1RX_RACC; /* 0xAC */
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unsigned int UART2TX_RACC; /* 0xB0 */
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unsigned int UART2RX_RACC; /* 0xB4 */
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unsigned int SDC_RACC; /* 0xB8 */
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unsigned int I2SAC97_RACC; /* 0xBC */
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unsigned int IRDATX_RACC; /* 0xC0 */
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unsigned int reserved4; /* 0xC4 */
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unsigned int USBD_RACC; /* 0xC8 */
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unsigned int IRDARX_RACC; /* 0xCC */
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unsigned int IRDA_RACC; /* 0xD0 */
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unsigned int ED0_RACC; /* 0xD4 */
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unsigned int ED1_RACC; /* 0xD8 */
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};
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/*
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* ID Number 0 Register
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*/
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#define FTPMU010_ID_A320A 0x03200000
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#define FTPMU010_ID_A320C 0x03200010
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#define FTPMU010_ID_A320D 0x03200030
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/*
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* OSC Control Register
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*/
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#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
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#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
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#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
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#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
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#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
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#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
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#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
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/*
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* Power Mode Register
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*/
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#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
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#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
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#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
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#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
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#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
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#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
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#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
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#define FTPMU010_PMODE_FCS (1 << 2)
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#define FTPMU010_PMODE_TURBO (1 << 1)
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#define FTPMU010_PMODE_SLEEP (1 << 0)
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/*
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* Power Manager Status Register
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*/
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#define FTPMU010_PMSR_SMR (1 << 10)
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#define FTPMU010_PMSR_RDH (1 << 2)
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#define FTPMU010_PMSR_PH (1 << 1)
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#define FTPMU010_PMSR_CKEHLOW (1 << 0)
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/*
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* Multi-Function Port Setting Register
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*/
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#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
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#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
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#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
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/*
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* PLL/DLL Control Register 0
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*/
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#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
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#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
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#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
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#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
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#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
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#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
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#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
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#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
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#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
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#endif /* __FTPMU010_H */
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