upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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225 lines
7.5 KiB
225 lines
7.5 KiB
18 years ago
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CPU_ASM_H
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#define _CPU_ASM_H
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#define BIT_C 0x00000001
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#define OP_BLR 0x4e800020
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#define OP_EXTSB 0x7c000774
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#define OP_EXTSH 0x7c000734
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#define OP_NEG 0x7c0000d0
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#define OP_CNTLZW 0x7c000034
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#define OP_ADD 0x7c000214
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#define OP_ADDC 0x7c000014
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#define OP_ADDME 0x7c0001d4
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#define OP_ADDZE 0x7c000194
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#define OP_ADDE 0x7c000114
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#define OP_ADDI 0x38000000
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#define OP_SUBF 0x7c000050
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#define OP_SUBFC 0x7c000010
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#define OP_SUBFE 0x7c000110
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#define OP_SUBFME 0x7c0001d0
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#define OP_SUBFZE 0x7c000190
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#define OP_MFCR 0x7c000026
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#define OP_MTCR 0x7c0ff120
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#define OP_MFXER 0x7c0102a6
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#define OP_MTXER 0x7c0103a6
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#define OP_MCRXR 0x7c000400
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#define OP_MCRF 0x4c000000
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#define OP_CRAND 0x4c000202
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#define OP_CRANDC 0x4c000102
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#define OP_CROR 0x4c000382
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#define OP_CRORC 0x4c000342
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#define OP_CRXOR 0x4c000182
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#define OP_CRNAND 0x4c0001c2
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#define OP_CRNOR 0x4c000042
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#define OP_CREQV 0x4c000242
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#define OP_CMPW 0x7c000000
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#define OP_CMPLW 0x7c000040
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#define OP_CMPWI 0x2c000000
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#define OP_CMPLWI 0x28000000
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#define OP_MULLW 0x7c0001d6
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#define OP_MULHW 0x7c000096
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#define OP_MULHWU 0x7c000016
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#define OP_DIVW 0x7c0003d6
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#define OP_DIVWU 0x7c000396
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#define OP_OR 0x7c000378
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#define OP_ORC 0x7c000338
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#define OP_XOR 0x7c000278
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#define OP_NAND 0x7c0003b8
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#define OP_NOR 0x7c0000f8
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#define OP_EQV 0x7c000238
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#define OP_SLW 0x7c000030
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#define OP_SRW 0x7c000430
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#define OP_SRAW 0x7c000630
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#define OP_ORI 0x60000000
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#define OP_ORIS 0x64000000
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#define OP_XORI 0x68000000
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#define OP_XORIS 0x6c000000
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#define OP_ANDI_ 0x70000000
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#define OP_ANDIS_ 0x74000000
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#define OP_SRAWI 0x7c000670
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#define OP_RLWINM 0x54000000
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#define OP_RLWNM 0x5c000000
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#define OP_RLWIMI 0x50000000
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#define OP_LWZ 0x80000000
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#define OP_LHZ 0xa0000000
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#define OP_LHA 0xa8000000
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#define OP_LBZ 0x88000000
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#define OP_LWZU 0x84000000
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#define OP_LHZU 0xa4000000
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#define OP_LHAU 0xac000000
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#define OP_LBZU 0x8c000000
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#define OP_LWZX 0x7c00002e
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#define OP_LHZX 0x7c00022e
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#define OP_LHAX 0x7c0002ae
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#define OP_LBZX 0x7c0000ae
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#define OP_LWZUX 0x7c00006e
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#define OP_LHZUX 0x7c00026e
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#define OP_LHAUX 0x7c0002ee
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#define OP_LBZUX 0x7c0000ee
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#define OP_STW 0x90000000
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#define OP_STH 0xb0000000
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#define OP_STB 0x98000000
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#define OP_STWU 0x94000000
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#define OP_STHU 0xb4000000
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#define OP_STBU 0x9c000000
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#define OP_STWX 0x7c00012e
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#define OP_STHX 0x7c00032e
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#define OP_STBX 0x7c0001ae
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#define OP_STWUX 0x7c00016e
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#define OP_STHUX 0x7c00036e
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#define OP_STBUX 0x7c0001ee
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#define OP_B 0x48000000
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#define OP_BL 0x48000001
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#define OP_BC 0x40000000
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#define OP_BCL 0x40000001
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#define OP_MTLR 0x7c0803a6
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#define OP_MFLR 0x7c0802a6
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#define OP_MTCTR 0x7c0903a6
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#define OP_MFCTR 0x7c0902a6
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#define OP_LMW 0xb8000000
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#define OP_STMW 0xbc000000
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#define OP_LSWI 0x7c0004aa
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#define OP_LSWX 0x7c00042a
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#define OP_STSWI 0x7c0005aa
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#define OP_STSWX 0x7c00052a
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#define ASM_0(opcode) (opcode)
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#define ASM_1(opcode, rd) ((opcode) + \
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((rd) << 21))
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#define ASM_1C(opcode, cr) ((opcode) + \
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((cr) << 23))
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#define ASM_11(opcode, rd, rs) ((opcode) + \
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((rd) << 21) + \
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((rs) << 16))
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#define ASM_11C(opcode, cd, cs) ((opcode) + \
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((cd) << 23) + \
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((cs) << 18))
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#define ASM_11X(opcode, rd, rs) ((opcode) + \
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((rs) << 21) + \
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((rd) << 16))
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#define ASM_11I(opcode, rd, rs, simm) ((opcode) + \
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((rd) << 21) + \
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((rs) << 16) + \
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((simm) & 0xffff))
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#define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \
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((rd) << 21) + \
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((rs) << 16) + \
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((simm) << 11))
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#define ASM_11S(opcode, rd, rs, sh) ((opcode) + \
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((rs) << 21) + \
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((rd) << 16) + \
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((sh) << 11))
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#define ASM_11IX(opcode, rd, rs, imm) ((opcode) + \
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((rs) << 21) + \
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((rd) << 16) + \
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((imm) & 0xffff))
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#define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \
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((rd) << 21) + \
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((rs1) << 16) + \
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((rs2) << 11))
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#define ASM_12F(opcode, fd, fs1, fs2) ((opcode) + \
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((fd) << 21) + \
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((fs1) << 16) + \
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((fs2) << 11))
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#define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \
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((rs1) << 21) + \
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((rd) << 16) + \
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((rs2) << 11))
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#define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \
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((cr) << 23) + \
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((rs1) << 16) + \
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((rs2) << 11))
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#define ASM_1IC(opcode, cr, rs, imm) ((opcode) + \
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((cr) << 23) + \
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((rs) << 16) + \
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((imm) & 0xffff))
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#define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \
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((opcode) + \
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((rs1) << 21) + \
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((rd) << 16) + \
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((rs2) << 11) + \
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((imm1) << 6) + \
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((imm2) << 1))
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#define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \
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((opcode) + \
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((rs) << 21) + \
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((rd) << 16) + \
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((imm1) << 11) + \
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((imm2) << 6) + \
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((imm3) << 1))
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#define ASM_1O(opcode, off) ((opcode) + (off))
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17 years ago
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#define ASM_3O(opcode, bo, bi, off) ((opcode) + \
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18 years ago
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((bo) << 21) + \
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((bi) << 16) + \
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(off))
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#define ASM_ADDI(rd, rs, simm) ASM_11I(OP_ADDI, rd, rs, simm)
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#define ASM_BLR ASM_0(OP_BLR)
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#define ASM_STW(rd, rs, simm) ASM_11I(OP_STW, rd, rs, simm)
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#define ASM_LWZ(rd, rs, simm) ASM_11I(OP_LWZ, rd, rs, simm)
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#define ASM_MFCR(rd) ASM_1(OP_MFCR, rd)
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#define ASM_MTCR(rd) ASM_1(OP_MTCR, rd)
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#define ASM_MFXER(rd) ASM_1(OP_MFXER, rd)
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#define ASM_MTXER(rd) ASM_1(OP_MTXER, rd)
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#define ASM_MFCTR(rd) ASM_1(OP_MFCTR, rd)
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#define ASM_MTCTR(rd) ASM_1(OP_MTCTR, rd)
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#define ASM_MCRXR(cr) ASM_1C(OP_MCRXR, cr)
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#define ASM_MCRF(cd, cs) ASM_11C(OP_MCRF, cd, cs)
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#define ASM_B(off) ASM_1O(OP_B, off)
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#define ASM_BL(off) ASM_1O(OP_BL, off)
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#define ASM_MFLR(rd) ASM_1(OP_MFLR, rd)
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#define ASM_MTLR(rd) ASM_1(OP_MTLR, rd)
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#define ASM_LI(rd, imm) ASM_ADDI(rd, 0, imm)
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#define ASM_LMW(rd, rs, simm) ASM_11I(OP_LMW, rd, rs, simm)
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#define ASM_STMW(rd, rs, simm) ASM_11I(OP_STMW, rd, rs, simm)
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#define ASM_LSWI(rd, rs, simm) ASM_11IF(OP_LSWI, rd, rs, simm)
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#define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2)
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#define ASM_STSWI(rd, rs, simm) ASM_11IF(OP_STSWI, rd, rs, simm)
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#define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2)
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#endif /* _CPU_ASM_H */
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