/ *
* Memory s u b - s y s t e m i n i t i a l i z a t i o n c o d e f o r I N C A - I P d e v e l o p m e n t b o a r d .
*
* Copyright ( c ) 2 0 0 3 W o l f g a n g D e n k < w d @denx.de>
*
* See f i l e C R E D I T S f o r l i s t o f p e o p l e w h o c o n t r i b u t e d t o t h i s
* project.
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version 2 of
* the L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* This p r o g r a m i s d i s t r i b u t e d i n t h e h o p e t h a t i t w i l l b e u s e f u l ,
* but W I T H O U T A N Y W A R R A N T Y ; without even the implied warranty of
* MERCHANTABILITY o r F I T N E S S F O R A P A R T I C U L A R P U R P O S E . S e e t h e
* GNU G e n e r a l P u b l i c L i c e n s e f o r m o r e d e t a i l s .
*
* You s h o u l d h a v e r e c e i v e d a c o p y o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* along w i t h t h i s p r o g r a m ; if not, write to the Free Software
* Foundation, I n c . , 5 9 T e m p l e P l a c e , S u i t e 3 3 0 , B o s t o n ,
* MA 0 2 1 1 1 - 1 3 0 7 U S A
* /
# include < c o n f i g . h >
# include < v e r s i o n . h >
# include < a s m / r e g d e f . h >
# define E B U _ M O D U L _ B A S E 0 x B 8 0 0 0 2 0 0
# define E B U _ C L C ( v a l u e ) 0 x00 0 0 ( v a l u e )
# define E B U _ C O N ( v a l u e ) 0 x00 1 0 ( v a l u e )
# define E B U _ A D D S E L 0 ( v a l u e ) 0 x00 2 0 ( v a l u e )
# define E B U _ A D D S E L 1 ( v a l u e ) 0 x00 2 4 ( v a l u e )
# define E B U _ A D D S E L 2 ( v a l u e ) 0 x00 2 8 ( v a l u e )
# define E B U _ B U S C O N 0 ( v a l u e ) 0 x00 6 0 ( v a l u e )
# define E B U _ B U S C O N 1 ( v a l u e ) 0 x00 6 4 ( v a l u e )
# define E B U _ B U S C O N 2 ( v a l u e ) 0 x00 6 8 ( v a l u e )
# define M C _ M O D U L _ B A S E 0 x B F 8 0 0 0 0 0
# define M C _ E R R C A U S E ( v a l u e ) 0 x01 0 0 ( v a l u e )
# define M C _ E R R A D D R ( v a l u e ) 0 x01 0 8 ( v a l u e )
# define M C _ I O G P ( v a l u e ) 0 x08 0 0 ( v a l u e )
# define M C _ S E L F R F S H ( v a l u e ) 0 x0 A 0 0 ( v a l u e )
# define M C _ C T R L E N A ( v a l u e ) 0 x10 0 0 ( v a l u e )
# define M C _ M R S C O D E ( v a l u e ) 0 x10 0 8 ( v a l u e )
# define M C _ C F G D W ( v a l u e ) 0 x10 1 0 ( v a l u e )
# define M C _ C F G P B 0 ( v a l u e ) 0 x10 1 8 ( v a l u e )
# define M C _ L A T E N C Y ( v a l u e ) 0 x10 3 8 ( v a l u e )
# define M C _ T R E F R E S H ( v a l u e ) 0 x10 4 0 ( v a l u e )
# define C G U _ M O D U L _ B A S E 0 x B F 1 0 7 0 0 0
# define C G U _ P L L 1 C R ( v a l u e ) 0 x00 0 8 ( v a l u e )
# define C G U _ D I V C R ( v a l u e ) 0 x00 1 0 ( v a l u e )
# define C G U _ M U X C R ( v a l u e ) 0 x00 1 4 ( v a l u e )
# define C G U _ P L L 1 S R ( v a l u e ) 0 x00 0 C ( v a l u e )
.set noreorder
/ *
* void e b u _ i n i t ( l o n g )
*
* a0 h a s t h e c l o c k v a l u e w e a r e g o i n g t o r u n a t
* /
.globl ebu_init
.ent ebu_init
ebu_init :
__ebu_init :
li t 1 , E B U _ M O D U L _ B A S E
li t 2 , 0 x A 0 0 0 0 0 4 1
sw t 2 , E B U _ A D D S E L 0 ( t 1 )
li t 2 , 0 x A 0 8 0 0 0 4 1
sw t 2 , E B U _ A D D S E L 2 ( t 1 )
li t 2 , 0 x B E 0 0 0 0 F 1
sw t 2 , E B U _ A D D S E L 1 ( t 1 )
li t 3 , 1 0 0 0 0 0 0 0 0
beq a0 , t 3 , 1 f
nop
li t 3 , 1 3 3 0 0 0 0 0 0
beq a0 , t 3 , 2 f
nop
li t 3 , 1 5 0 0 0 0 0 0 0
beq a0 , t 3 , 2 f
nop
b 3 f
nop
/* 100 MHz */
1 :
li t 2 , 0 x88 4 1 4 1 7 D
sw t 2 , E B U _ B U S C O N 0 ( t 1 )
sw t 2 , E B U _ B U S C O N 2 ( t 1 )
li t 2 , 0 x68 4 1 4 2 B D
b 3 f
sw t 2 , E B U _ B U S C O N 1 ( t 1 ) / * d e l a y s l o t * /
/* 133 or 150 MHz */
2 :
li t 2 , 0 x88 4 1 4 1 7 E
sw t 2 , E B U _ B U S C O N 0 ( t 1 )
sw t 2 , E B U _ B U S C O N 2 ( t 1 )
li t 2 , 0 x68 4 1 4 3 F D
sw t 2 , E B U _ B U S C O N 1 ( t 1 )
3 :
jr r a
nop
.end ebu_init
/ *
* void c g u _ i n i t ( l o n g )
*
* a0 h a s t h e c l o c k v a l u e
* /
.globl cgu_init
.ent cgu_init
cgu_init :
__cgu_init :
li t 1 , C G U _ M O D U L _ B A S E
li t 3 , 1 0 0 0 0 0 0 0 0
beq a0 , t 3 , 1 f
nop
li t 3 , 1 3 3 0 0 0 0 0 0
beq a0 , t 3 , 2 f
nop
li t 3 , 1 5 0 0 0 0 0 0 0
beq a0 , t 3 , 3 f
nop
b 5 f
nop
/* 100 MHz clock */
1 :
li t 2 , 0 x80 0 0 0 0 1 4
sw t 2 , C G U _ D I V C R ( t 1 )
li t 2 , 0 x80 0 0 0 0 0 0
sw t 2 , C G U _ M U X C R ( t 1 )
li t 2 , 0 x80 0 B 0 0 0 1
b 5 f
sw t 2 , C G U _ P L L 1 C R ( t 1 ) / * d e l a y s l o t * /
/* 133 MHz clock */
2 :
li t 2 , 0 x80 0 0 0 0 5 4
sw t 2 , C G U _ D I V C R ( t 1 )
li t 2 , 0 x80 0 0 0 0 0 0
sw t 2 , C G U _ M U X C R ( t 1 )
li t 2 , 0 x80 0 B 0 0 0 1
b 5 f
sw t 2 , C G U _ P L L 1 C R ( t 1 ) / * d e l a y s l o t * /
/* 150 MHz clock */
3 :
li t 2 , 0 x80 0 0 0 0 1 7
sw t 2 , C G U _ D I V C R ( t 1 )
li t 2 , 0 x C 0 0 B 0 0 0 1
sw t 2 , C G U _ P L L 1 C R ( t 1 )
li t 3 , 0 x80 0 0 0 0 0 0
4 :
lw t 2 , C G U _ P L L 1 S R ( t 1 )
and t 2 , t 2 , t 3
beq t 2 , z e r o , 4 b
nop
li t 2 , 0 x80 0 0 0 0 0 1
sw t 2 , C G U _ M U X C R ( t 1 )
5 :
jr r a
nop
.end cgu_init
/ *
* void s d r a m _ i n i t ( l o n g )
*
* a0 h a s t h e c l o c k v a l u e
* /
.globl sdram_init
.ent sdram_init
sdram_init :
__sdram_init :
li t 1 , M C _ M O D U L _ B A S E
# if 0
/* Disable memory controller before changing any of its registers */
sw z e r o , M C _ C T R L E N A ( t 1 )
# endif
li t 2 , 1 0 0 0 0 0 0 0 0
beq a0 , t 2 , 1 f
nop
li t 2 , 1 3 3 0 0 0 0 0 0
beq a0 , t 2 , 2 f
nop
li t 2 , 1 5 0 0 0 0 0 0 0
beq a0 , t 2 , 3 f
nop
b 5 f
nop
/* 100 MHz clock */
1 :
/* Set clock ratio (clkrat=1:1, rddel=3) */
li t 2 , 0 x00 0 0 0 0 0 3
sw t 2 , M C _ I O G P ( t 1 )
/* Set sdram refresh rate (4K/64ms @ 100MHz) */
li t 2 , 0 x00 0 0 0 6 1 A
b 4 f
sw t 2 , M C _ T R E F R E S H ( t 1 )
/* 133 MHz clock */
2 :
/* Set clock ratio (clkrat=1:1, rddel=3) */
li t 2 , 0 x00 0 0 0 0 0 3
sw t 2 , M C _ I O G P ( t 1 )
/* Set sdram refresh rate (4K/64ms @ 133MHz) */
li t 2 , 0 x00 0 0 0 8 2 2
b 4 f
sw t 2 , M C _ T R E F R E S H ( t 1 )
/* 150 MHz clock */
3 :
/* Set clock ratio (clkrat=3:2, rddel=4) */
li t 2 , 0 x00 0 0 0 0 1 4
sw t 2 , M C _ I O G P ( t 1 )
/* Set sdram refresh rate (4K/64ms @ 150MHz) */
li t 2 , 0 x00 0 0 0 9 2 7
sw t 2 , M C _ T R E F R E S H ( t 1 )
4 :
/* Clear Error log registers */
sw z e r o , M C _ E R R C A U S E ( t 1 )
sw z e r o , M C _ E R R A D D R ( t 1 )
/* Clear Power-down registers */
sw z e r o , M C _ S E L F R F S H ( t 1 )
/* Set CAS Latency */
li t 2 , 0 x00 0 0 0 0 2 0 / * C L = 2 * /
sw t 2 , M C _ M R S C O D E ( t 1 )
/* Set word width to 16 bit */
li t 2 , 0 x2
sw t 2 , M C _ C F G D W ( t 1 )
/* Set CS0 to SDRAM parameters */
li t 2 , 0 x00 0 0 1 4 C 9
sw t 2 , M C _ C F G P B 0 ( t 1 )
/* Set SDRAM latency parameters */
li t 2 , 0 x00 0 2 6 3 2 5 / * B C P C 1 0 0 * /
sw t 2 , M C _ L A T E N C Y ( t 1 )
5 :
/* Finally enable the controller */
li t 2 , 0 x00 0 0 0 0 0 1
sw t 2 , M C _ C T R L E N A ( t 1 )
jr r a
nop
.end sdram_init
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init :
/ * Disable W a t c h d o g .
* /
la t 9 , d i s a b l e _ i n c a i p _ w d t
jalr t 9
nop
/ * EBU, C G U a n d S D R A M I n i t i a l i z a t i o n .
* /
li a0 , C P U _ C L O C K _ R A T E
move t 0 , r a
/ * We r e l y o n t h e f a c t t h a t n e i t h e r e b u _ i n i t ( ) n o r c g u _ i n i t ( ) n o r s d r a m _ i n i t ( )
* modify t 0 a n d a0 .
* /
bal _ _ c g u _ i n i t
nop
bal _ _ e b u _ i n i t
nop
bal _ _ s d r a m _ i n i t
nop
move r a , t 0
jr r a
nop
.end lowlevel_init