upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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97 lines
2.4 KiB
97 lines
2.4 KiB
19 years ago
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/* By Thomas.Lange@Corelatus.com 001025 */
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/* Definitions for EEPROM/VOLT METER DS2438 */
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/* Copyright (C) 2000-2005 Corelatus AB */
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/* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef INCeedevh
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#define INCeedevh
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#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
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/* MIPS */
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#define WRITE_PORT(Value) write_gpio_data(Value)
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#define READ_PORT (gpio_read()&GPIO_EEDQ)
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/* 64 bytes chip */
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#define EE_CHIP_SIZE 64
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/* Board with new current resistor */
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#define EE_GTH_0304 1
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/* new dsp and 64 MB SDRAM */
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#define EE_DSP_64 0x10
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/* microsecs */
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/* Pull line down at least this long for reset pulse */
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#define RESET_LOW_TIME 490
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/* Read presence pulse after we release reset pulse */
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#define PRESENCE_TIMEOUT 100
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#define PRESENCE_LOW_TIME 200
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#define WRITE_0_LOW 60
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#define WRITE_1_LOW 1
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#define TOTAL_WRITE_LOW 60
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#define READ_LOW 1
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#define READ_TIMEOUT 10
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#define TOTAL_READ_LOW 70
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/* Rom function commands */
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#define READ_ROM 0x33
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#define MATCH_ROM 0x55
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#define SKIP_ROM 0xCC
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#define SEARCH_ROM 0xF0
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/* Memory_command_function */
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#define WRITE_SCRATCHPAD 0x4E
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#define READ_SCRATCHPAD 0xBE
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#define COPY_SCRATCHPAD 0x48
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#define RECALL_MEMORY 0xB8
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#define CONVERT_TEMP 0x44
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#define CONVERT_VOLTAGE 0xB4
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/* Chip is divided in 8 pages, 8 bytes each */
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#define EE_PAGE_SIZE 8
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/* All chip data we want are in page 0 */
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/* Bytes in page 0 */
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#define EE_P0_STATUS 0
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#define EE_P0_TEMP_LSB 1
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#define EE_P0_TEMP_MSB 2
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#define EE_P0_VOLT_LSB 3
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#define EE_P0_VOLT_MSB 4
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#define EE_P0_CURRENT_LSB 5
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#define EE_P0_CURRENT_MSB 6
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/* 40 byte user data is located at page 3-7 */
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#define EE_USER_PAGE_0 3
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#define USER_PAGES 5
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/* Layout of gth user pages usage */
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/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */
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#define EE_ETHERNET_OFFSET 0
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#endif /* INCeedevh */
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