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@ -126,8 +126,6 @@ static int ich_init_controller(struct udevice *dev, |
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if (plat->ich_version == ICHV_7) { |
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struct ich7_spi_regs *ich7_spi = sbase; |
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ich7_spi = (struct ich7_spi_regs *)sbase; |
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ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; |
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ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); |
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ctlr->menubytes = sizeof(ich7_spi->opmenu); |
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ctlr->optype = offsetof(struct ich7_spi_regs, optype); |
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@ -142,7 +140,6 @@ static int ich_init_controller(struct udevice *dev, |
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} else if (plat->ich_version == ICHV_9) { |
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struct ich9_spi_regs *ich9_spi = sbase; |
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ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; |
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ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); |
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ctlr->menubytes = sizeof(ich9_spi->opmenu); |
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ctlr->optype = offsetof(struct ich9_spi_regs, optype); |
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@ -187,6 +184,23 @@ static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) |
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trans->bytesin -= bytes; |
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} |
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static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase) |
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{ |
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int lock = 0; |
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if (plat->ich_version == ICHV_7) { |
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struct ich7_spi_regs *ich7_spi = sbase; |
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lock = readw(&ich7_spi->spis) & SPIS_LOCK; |
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} else if (plat->ich_version == ICHV_9) { |
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struct ich9_spi_regs *ich9_spi = sbase; |
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lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; |
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} |
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return lock != 0; |
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} |
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static void spi_setup_type(struct spi_trans *trans, int data_bytes) |
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{ |
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trans->type = 0xFF; |
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@ -220,14 +234,15 @@ static void spi_setup_type(struct spi_trans *trans, int data_bytes) |
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} |
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} |
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static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) |
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static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, |
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bool lock) |
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{ |
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uint16_t optypes; |
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uint8_t opmenu[ctlr->menubytes]; |
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trans->opcode = trans->out[0]; |
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spi_use_out(trans, 1); |
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if (!ctlr->ichspi_lock) { |
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if (!lock) { |
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/* The lock is off, so just use index 0. */ |
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ich_writeb(ctlr, trans->opcode, ctlr->opmenu); |
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optypes = ich_readw(ctlr, ctlr->optype); |
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@ -323,6 +338,21 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, |
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return -ETIMEDOUT; |
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} |
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void ich_spi_config_opcode(struct udevice *dev) |
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{ |
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struct ich_spi_priv *ctlr = dev_get_priv(dev); |
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/*
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* PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down |
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* to prevent accidental or intentional writes. Before they get |
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* locked down, these registers should be initialized properly. |
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*/ |
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ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); |
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ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); |
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ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); |
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ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); |
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} |
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static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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const void *dout, void *din, unsigned long flags) |
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{ |
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@ -337,6 +367,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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struct spi_trans *trans = &ctlr->trans; |
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unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); |
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int using_cmd = 0; |
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bool lock = spi_lock_status(plat, ctlr->base); |
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int ret; |
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/* We don't support writing partial bytes */ |
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@ -400,7 +431,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); |
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spi_setup_type(trans, using_cmd ? bytes : 0); |
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opcode_index = spi_setup_opcode(ctlr, trans); |
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opcode_index = spi_setup_opcode(ctlr, trans, lock); |
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if (opcode_index < 0) |
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return -EINVAL; |
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with_address = spi_setup_offset(trans); |
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@ -413,7 +444,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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* in order to prevent the Management Engine from |
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* issuing a transaction between WREN and DATA. |
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*/ |
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if (!ctlr->ichspi_lock) |
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if (!lock) |
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ich_writew(ctlr, trans->opcode, ctlr->preop); |
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return 0; |
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} |
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@ -539,56 +570,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, |
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return 0; |
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} |
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/*
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* This uses the SPI controller from the Intel Cougar Point and Panther Point |
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* PCH to write-protect portions of the SPI flash until reboot. The changes |
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* don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's |
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* done elsewhere. |
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*/ |
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int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, |
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uint32_t length, int hint) |
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{ |
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struct udevice *bus = dev->parent; |
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struct ich_spi_priv *ctlr = dev_get_priv(bus); |
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uint32_t tmplong; |
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uint32_t upper_limit; |
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if (!ctlr->pr) { |
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printf("%s: operation not supported on this chipset\n", |
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__func__); |
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return -ENOSYS; |
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} |
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if (length == 0 || |
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lower_limit > (0xFFFFFFFFUL - length) + 1 || |
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hint < 0 || hint > 4) { |
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printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, |
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lower_limit, length, hint); |
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return -EPERM; |
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} |
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upper_limit = lower_limit + length - 1; |
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/*
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* Determine bits to write, as follows: |
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* 31 Write-protection enable (includes erase operation) |
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* 30:29 reserved |
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* 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) |
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* 15 Read-protection enable |
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* 14:13 reserved |
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* 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) |
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*/ |
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tmplong = 0x80000000 | |
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((upper_limit & 0x01fff000) << 4) | |
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((lower_limit & 0x01fff000) >> 12); |
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printf("%s: writing 0x%08x to %p\n", __func__, tmplong, |
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&ctlr->pr[hint]); |
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ctlr->pr[hint] = tmplong; |
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return 0; |
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} |
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static int ich_spi_probe(struct udevice *dev) |
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{ |
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struct ich_spi_platdata *plat = dev_get_platdata(dev); |
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@ -619,16 +600,11 @@ static int ich_spi_probe(struct udevice *dev) |
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static int ich_spi_remove(struct udevice *bus) |
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{ |
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struct ich_spi_priv *ctlr = dev_get_priv(bus); |
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/*
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* Configure SPI controller so that the Linux MTD driver can fully |
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* access the SPI NOR chip |
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*/ |
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ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); |
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ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); |
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ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); |
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ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); |
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ich_spi_config_opcode(bus); |
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return 0; |
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} |
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Tom Rini
7 years ago