This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>master
Masahiro Yamada
7 years ago
parent
213fcabdfd
commit
00aa453ebf
@ -1,100 +0,0 @@ |
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/* |
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* Device Tree Source for UniPhier sLD3 Reference Board |
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* |
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* Copyright (C) 2015-2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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*/ |
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|
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/dts-v1/; |
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/include/ "uniphier-sld3.dtsi" |
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/include/ "uniphier-ref-daughter.dtsi" |
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/include/ "uniphier-support-card.dtsi" |
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/ { |
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model = "UniPhier sLD3 Reference Board"; |
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compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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aliases { |
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serial0 = &serial0; |
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serial1 = &serial1; |
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serial2 = &serial2; |
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i2c0 = &i2c0; |
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i2c1 = &i2c1; |
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i2c2 = &i2c2; |
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i2c3 = &i2c3; |
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i2c4 = &i2c4; |
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}; |
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|
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memory@8000000 { |
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device_type = "memory"; |
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reg = <0x80000000 0x20000000 |
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0xc0000000 0x20000000>; |
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}; |
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}; |
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|
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ðsc { |
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interrupts = <0 49 4>; |
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}; |
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&serial0 { |
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status = "okay"; |
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}; |
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&serial1 { |
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status = "okay"; |
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}; |
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|
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&serial2 { |
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status = "okay"; |
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}; |
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&i2c0 { |
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status = "okay"; |
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}; |
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&emmc { |
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status = "okay"; |
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}; |
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&sd { |
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status = "okay"; |
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}; |
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&usb0 { |
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status = "okay"; |
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}; |
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&usb1 { |
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status = "okay"; |
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}; |
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&usb2 { |
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status = "okay"; |
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}; |
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&usb3 { |
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status = "okay"; |
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}; |
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|
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/* for U-Boot only */ |
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&serial0 { |
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u-boot,dm-pre-reloc; |
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}; |
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&emmc { |
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u-boot,dm-pre-reloc; |
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}; |
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&pinctrl_uart0 { |
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u-boot,dm-pre-reloc; |
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}; |
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&pinctrl_emmc { |
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u-boot,dm-pre-reloc; |
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}; |
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@ -1,458 +0,0 @@ |
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/* |
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* Device Tree Source for UniPhier sLD3 SoC |
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* |
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* Copyright (C) 2015-2016 Socionext Inc. |
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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*/ |
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/ { |
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compatible = "socionext,uniphier-sld3"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a9"; |
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reg = <0>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a9"; |
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reg = <1>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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clocks { |
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refclk: ref { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <24576000>; |
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}; |
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arm_timer_clk: arm_timer_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <50000000>; |
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}; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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interrupt-parent = <&intc>; |
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u-boot,dm-pre-reloc; |
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timer@20000200 { |
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compatible = "arm,cortex-a9-global-timer"; |
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reg = <0x20000200 0x20>; |
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interrupts = <1 11 0x304>; |
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clocks = <&arm_timer_clk>; |
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}; |
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timer@20000600 { |
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compatible = "arm,cortex-a9-twd-timer"; |
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reg = <0x20000600 0x20>; |
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interrupts = <1 13 0x304>; |
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clocks = <&arm_timer_clk>; |
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}; |
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intc: interrupt-controller@20001000 { |
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compatible = "arm,cortex-a9-gic"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x20001000 0x1000>, |
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<0x20000100 0x100>; |
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}; |
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l2: l2-cache@500c0000 { |
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compatible = "socionext,uniphier-system-cache"; |
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, |
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<0x506c0000 0x400>; |
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interrupts = <0 174 4>, <0 175 4>; |
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cache-unified; |
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cache-size = <(512 * 1024)>; |
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cache-sets = <256>; |
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cache-line-size = <128>; |
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cache-level = <2>; |
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}; |
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serial0: serial@54006800 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006800 0x40>; |
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interrupts = <0 33 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart0>; |
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clocks = <&sys_clk 0>; |
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clock-frequency = <36864000>; |
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}; |
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serial1: serial@54006900 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006900 0x40>; |
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interrupts = <0 35 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart1>; |
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clocks = <&sys_clk 0>; |
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clock-frequency = <36864000>; |
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}; |
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serial2: serial@54006a00 { |
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compatible = "socionext,uniphier-uart"; |
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status = "disabled"; |
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reg = <0x54006a00 0x40>; |
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interrupts = <0 37 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart2>; |
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clocks = <&sys_clk 0>; |
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clock-frequency = <36864000>; |
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}; |
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port0x: gpio@55000008 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000008 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port1x: gpio@55000010 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000010 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port2x: gpio@55000018 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000018 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port3x: gpio@55000020 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000020 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port4: gpio@55000028 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000028 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port5x: gpio@55000030 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000030 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port6x: gpio@55000038 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000038 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port7x: gpio@55000040 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000040 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port8x: gpio@55000048 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000048 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port9x: gpio@55000050 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000050 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port10x: gpio@55000058 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000058 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port11x: gpio@55000060 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000060 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port12x: gpio@55000068 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000068 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port13x: gpio@55000070 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000070 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port14x: gpio@55000078 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000078 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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port16x: gpio@55000088 { |
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compatible = "socionext,uniphier-gpio"; |
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reg = <0x55000088 0x8>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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i2c0: i2c@58400000 { |
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compatible = "socionext,uniphier-i2c"; |
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status = "disabled"; |
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reg = <0x58400000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 41 1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c0>; |
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clocks = <&sys_clk 1>; |
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clock-frequency = <100000>; |
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}; |
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i2c1: i2c@58480000 { |
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compatible = "socionext,uniphier-i2c"; |
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status = "disabled"; |
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reg = <0x58480000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 42 1>; |
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clocks = <&sys_clk 1>; |
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clock-frequency = <100000>; |
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}; |
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i2c2: i2c@58500000 { |
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compatible = "socionext,uniphier-i2c"; |
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status = "disabled"; |
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reg = <0x58500000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 43 1>; |
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clocks = <&sys_clk 1>; |
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clock-frequency = <100000>; |
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}; |
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i2c3: i2c@58580000 { |
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compatible = "socionext,uniphier-i2c"; |
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status = "disabled"; |
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reg = <0x58580000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 44 1>; |
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clocks = <&sys_clk 1>; |
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clock-frequency = <100000>; |
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}; |
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/* chip-internal connection for DMD */ |
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i2c4: i2c@58600000 { |
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compatible = "socionext,uniphier-i2c"; |
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reg = <0x58600000 0x40>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <0 45 1>; |
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clocks = <&sys_clk 1>; |
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clock-frequency = <400000>; |
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}; |
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system_bus: system-bus@58c00000 { |
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compatible = "socionext,uniphier-system-bus"; |
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status = "disabled"; |
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reg = <0x58c00000 0x400>; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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}; |
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smpctrl@59801000 { |
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compatible = "socionext,uniphier-smpctrl"; |
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reg = <0x59801000 0x400>; |
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}; |
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mioctrl@59810000 { |
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compatible = "socionext,uniphier-sld3-mioctrl", |
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"simple-mfd", "syscon"; |
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reg = <0x59810000 0x800>; |
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u-boot,dm-pre-reloc; |
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mio_clk: clock { |
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compatible = "socionext,uniphier-sld3-mio-clock"; |
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#clock-cells = <1>; |
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u-boot,dm-pre-reloc; |
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}; |
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mio_rst: reset { |
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compatible = "socionext,uniphier-sld3-mio-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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emmc: sdhc@5a400000 { |
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compatible = "socionext,uniphier-sdhc"; |
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status = "disabled"; |
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reg = <0x5a400000 0x200>; |
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interrupts = <0 78 4>; |
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pinctrl-names = "default", "1.8v"; |
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pinctrl-0 = <&pinctrl_emmc>; |
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pinctrl-1 = <&pinctrl_emmc_1v8>; |
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clocks = <&mio_clk 1>; |
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reset-names = "host", "bridge"; |
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resets = <&mio_rst 1>, <&mio_rst 4>; |
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bus-width = <8>; |
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non-removable; |
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cap-mmc-highspeed; |
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cap-mmc-hw-reset; |
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}; |
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sd: sdhc@5a500000 { |
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compatible = "socionext,uniphier-sdhc"; |
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status = "disabled"; |
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reg = <0x5a500000 0x200>; |
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interrupts = <0 76 4>; |
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pinctrl-names = "default", "1.8v"; |
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pinctrl-0 = <&pinctrl_sd>; |
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pinctrl-1 = <&pinctrl_sd_1v8>; |
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clocks = <&mio_clk 0>; |
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reset-names = "host", "bridge"; |
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resets = <&mio_rst 0>, <&mio_rst 3>; |
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bus-width = <4>; |
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cap-sd-highspeed; |
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sd-uhs-sdr12; |
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sd-uhs-sdr25; |
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sd-uhs-sdr50; |
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}; |
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usb0: usb@5a800100 { |
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compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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status = "disabled"; |
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reg = <0x5a800100 0x100>; |
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interrupts = <0 80 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb0>; |
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clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, |
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<&mio_rst 12>; |
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}; |
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usb1: usb@5a810100 { |
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compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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status = "disabled"; |
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reg = <0x5a810100 0x100>; |
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interrupts = <0 81 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb1>; |
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clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, |
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<&mio_rst 13>; |
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}; |
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usb2: usb@5a820100 { |
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compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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status = "disabled"; |
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reg = <0x5a820100 0x100>; |
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interrupts = <0 82 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb2>; |
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clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, |
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<&mio_rst 14>; |
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}; |
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usb3: usb@5a830100 { |
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compatible = "socionext,uniphier-ehci", "generic-ehci"; |
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status = "disabled"; |
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reg = <0x5a830100 0x100>; |
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interrupts = <0 83 4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb3>; |
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clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; |
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, |
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<&mio_rst 15>; |
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}; |
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|
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soc-glue@5f800000 { |
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compatible = "socionext,uniphier-sld3-soc-glue", |
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"simple-mfd", "syscon"; |
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reg = <0x5f800000 0x2000>; |
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u-boot,dm-pre-reloc; |
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pinctrl: pinctrl { |
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compatible = "socionext,uniphier-sld3-pinctrl"; |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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aidet@f1830000 { |
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compatible = "simple-mfd", "syscon"; |
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reg = <0xf1830000 0x200>; |
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}; |
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sysctrl@f1840000 { |
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compatible = "socionext,uniphier-sld3-sysctrl", |
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"simple-mfd", "syscon"; |
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reg = <0xf1840000 0x10000>; |
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|
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sys_clk: clock { |
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compatible = "socionext,uniphier-sld3-clock"; |
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#clock-cells = <1>; |
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}; |
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|
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sys_rst: reset { |
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compatible = "socionext,uniphier-sld3-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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|
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nand: nand@f8000000 { |
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compatible = "socionext,uniphier-denali-nand-v5a"; |
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status = "disabled"; |
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reg-names = "nand_data", "denali_reg"; |
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reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; |
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interrupts = <0 65 4>; |
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clocks = <&sys_clk 2>; |
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nand-ecc-strength = <8>; |
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}; |
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}; |
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}; |
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|
||||
/include/ "uniphier-pinctrl.dtsi" |
||||
@ -1,39 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2014 Panasonic Corporation |
||||
* Copyright (C) 2015-2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <linux/io.h> |
||||
|
||||
#include "../init.h" |
||||
#include "bcu-regs.h" |
||||
|
||||
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) |
||||
|
||||
void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
int shift; |
||||
|
||||
writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ |
||||
writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ |
||||
writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ |
||||
/*
|
||||
* 0xe0000000-0xefffffff: Ex-bus |
||||
* 0xf0000000-0xfbffffff: ASM bus |
||||
* 0xfc000000-0xffffffff: OCM bus |
||||
*/ |
||||
writel(0x24440000, BCSCR5); |
||||
|
||||
/* Specify DDR channel */ |
||||
shift = bd->dram_ch[0].size / 0x04000000 * 4; |
||||
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ |
||||
|
||||
shift -= 32; |
||||
writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ |
||||
|
||||
shift -= 32; |
||||
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ |
||||
} |
||||
@ -1,84 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Panasonic Corporation |
||||
* Copyright (C) 2015-2017 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
#include <linux/io.h> |
||||
#include <linux/kernel.h> |
||||
|
||||
#include "boot-device.h" |
||||
|
||||
const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = { |
||||
{BOOT_DEVICE_NOR, "NOR (XECS0)"}, |
||||
{BOOT_DEVICE_NONE, "External Master"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
{BOOT_DEVICE_NONE, "Reserved"}, |
||||
}; |
||||
|
||||
const unsigned uniphier_sld3_boot_device_count = |
||||
ARRAY_SIZE(uniphier_sld3_boot_device_table); |
||||
@ -1,13 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "../init.h" |
||||
|
||||
int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
/* add pll init code here */ |
||||
return 0; |
||||
} |
||||
@ -1,14 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "../init.h" |
||||
#include "pll.h" |
||||
|
||||
void uniphier_sld3_pll_init(void) |
||||
{ |
||||
uniphier_ld4_dpll_ssc_en(); |
||||
} |
||||
@ -1,31 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <linux/kernel.h> |
||||
#include <linux/io.h> |
||||
|
||||
#include "../bcu/bcu-regs.h" |
||||
#include "../sc-regs.h" |
||||
#include "../sg-regs.h" |
||||
#include "debug-uart.h" |
||||
|
||||
#define UNIPHIER_SLD3_UART_CLK 36864000 |
||||
|
||||
unsigned int uniphier_sld3_debug_uart_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
sg_set_pinsel(64, 1, 4, 4); /* TXD0 -> TXD0 */ |
||||
|
||||
writel(0x24440000, BCSCR5); |
||||
|
||||
tmp = readl(SC_CLKCTRL); |
||||
tmp |= SC_CLKCTRL_CEN_PERI; |
||||
writel(tmp, SC_CLKCTRL); |
||||
|
||||
return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE); |
||||
} |
||||
@ -1,6 +0,0 @@ |
||||
#include "../init.h" |
||||
|
||||
int uniphier_sld3_umc_init(const struct uniphier_board_data *bd) |
||||
{ |
||||
return 0; |
||||
} |
||||
@ -1,46 +0,0 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_UNIPHIER=y |
||||
CONFIG_SYS_TEXT_BASE=0x84000000 |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_SPL_MMC_SUPPORT=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_NAND_SUPPORT=y |
||||
CONFIG_ARCH_UNIPHIER_SLD3=y |
||||
CONFIG_MICRO_SUPPORT_CARD=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref" |
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_NOR_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_CONFIG=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_GPT=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_TFTPPUT=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_TIME=y |
||||
# CONFIG_CMD_MISC is not set |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
# CONFIG_SPL_DOS_PARTITION is not set |
||||
# CONFIG_SPL_EFI_PARTITION is not set |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_GPIO_UNIPHIER=y |
||||
CONFIG_MISC=y |
||||
CONFIG_I2C_EEPROM=y |
||||
CONFIG_MMC_UNIPHIER=y |
||||
CONFIG_NAND_DENALI=y |
||||
CONFIG_SYS_NAND_DENALI_64BIT=y |
||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 |
||||
CONFIG_SPL_NAND_DENALI=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_EHCI_GENERIC=y |
||||
CONFIG_USB_STORAGE=y |
||||
@ -1,129 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Socionext Inc. |
||||
* Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <dm/pinctrl.h> |
||||
|
||||
#include "pinctrl-uniphier.h" |
||||
|
||||
static const unsigned emmc_pins[] = {55, 56, 60}; |
||||
static const int emmc_muxvals[] = {1, 1, 1}; |
||||
static const unsigned emmc_dat8_pins[] = {57}; |
||||
static const int emmc_dat8_muxvals[] = {1}; |
||||
static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112, |
||||
113}; |
||||
static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2}; |
||||
static const unsigned ether_rmii_pins[] = {35}; |
||||
static const int ether_rmii_muxvals[] = {1}; |
||||
static const unsigned i2c0_pins[] = {36}; |
||||
static const int i2c0_muxvals[] = {0}; |
||||
static const unsigned nand_pins[] = {38, 39, 40, 58, 59}; |
||||
static const int nand_muxvals[] = {1, 1, 1, 1, 1}; |
||||
static const unsigned nand_cs1_pins[] = {41}; |
||||
static const int nand_cs1_muxvals[] = {1}; |
||||
static const unsigned sd_pins[] = {42, 43, 44, 45}; |
||||
static const int sd_muxvals[] = {1, 1, 1, 1}; |
||||
static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76, |
||||
77, 78, 79, 80, 88, 89, 91, 92, 99}; |
||||
static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
||||
1, 1, 1, 1, 1}; |
||||
static const unsigned system_bus_cs0_pins[] = {93}; |
||||
static const int system_bus_cs0_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs1_pins[] = {94}; |
||||
static const int system_bus_cs1_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs2_pins[] = {95}; |
||||
static const int system_bus_cs2_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs3_pins[] = {96}; |
||||
static const int system_bus_cs3_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs4_pins[] = {81}; |
||||
static const int system_bus_cs4_muxvals[] = {1}; |
||||
static const unsigned system_bus_cs5_pins[] = {82}; |
||||
static const int system_bus_cs5_muxvals[] = {1}; |
||||
static const unsigned uart0_pins[] = {63, 64}; |
||||
static const int uart0_muxvals[] = {0, 1}; |
||||
static const unsigned uart1_pins[] = {65, 66}; |
||||
static const int uart1_muxvals[] = {0, 1}; |
||||
static const unsigned uart2_pins[] = {96, 102}; |
||||
static const int uart2_muxvals[] = {2, 2}; |
||||
static const unsigned usb0_pins[] = {13, 14}; |
||||
static const int usb0_muxvals[] = {0, 1}; |
||||
static const unsigned usb1_pins[] = {15, 16}; |
||||
static const int usb1_muxvals[] = {0, 1}; |
||||
static const unsigned usb2_pins[] = {17, 18}; |
||||
static const int usb2_muxvals[] = {0, 1}; |
||||
static const unsigned usb3_pins[] = {19, 20}; |
||||
static const int usb3_muxvals[] = {0, 1}; |
||||
|
||||
static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = { |
||||
UNIPHIER_PINCTRL_GROUP_SPL(emmc), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8), |
||||
UNIPHIER_PINCTRL_GROUP(ether_mii), |
||||
UNIPHIER_PINCTRL_GROUP(ether_rmii), |
||||
UNIPHIER_PINCTRL_GROUP(i2c0), |
||||
UNIPHIER_PINCTRL_GROUP(nand), |
||||
UNIPHIER_PINCTRL_GROUP(nand_cs1), |
||||
UNIPHIER_PINCTRL_GROUP(sd), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs0), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs1), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs2), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs3), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs4), |
||||
UNIPHIER_PINCTRL_GROUP(system_bus_cs5), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(uart0), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(uart1), |
||||
UNIPHIER_PINCTRL_GROUP_SPL(uart2), |
||||
UNIPHIER_PINCTRL_GROUP(usb0), |
||||
UNIPHIER_PINCTRL_GROUP(usb1), |
||||
UNIPHIER_PINCTRL_GROUP(usb2), |
||||
UNIPHIER_PINCTRL_GROUP(usb3) |
||||
}; |
||||
|
||||
static const char * const uniphier_sld3_functions[] = { |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(emmc), |
||||
UNIPHIER_PINMUX_FUNCTION(ether_mii), |
||||
UNIPHIER_PINMUX_FUNCTION(ether_rmii), |
||||
UNIPHIER_PINMUX_FUNCTION(i2c0), |
||||
UNIPHIER_PINMUX_FUNCTION(nand), |
||||
UNIPHIER_PINMUX_FUNCTION(sd), |
||||
UNIPHIER_PINMUX_FUNCTION(system_bus), |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(uart0), |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(uart1), |
||||
UNIPHIER_PINMUX_FUNCTION_SPL(uart2), |
||||
UNIPHIER_PINMUX_FUNCTION(usb0), |
||||
UNIPHIER_PINMUX_FUNCTION(usb1), |
||||
UNIPHIER_PINMUX_FUNCTION(usb2), |
||||
UNIPHIER_PINMUX_FUNCTION(usb3), |
||||
}; |
||||
|
||||
static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = { |
||||
.groups = uniphier_sld3_groups, |
||||
.groups_count = ARRAY_SIZE(uniphier_sld3_groups), |
||||
.functions = uniphier_sld3_functions, |
||||
.functions_count = ARRAY_SIZE(uniphier_sld3_functions), |
||||
.caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT, |
||||
}; |
||||
|
||||
static int uniphier_sld3_pinctrl_probe(struct udevice *dev) |
||||
{ |
||||
return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata); |
||||
} |
||||
|
||||
static const struct udevice_id uniphier_sld3_pinctrl_match[] = { |
||||
{ .compatible = "socionext,uniphier-sld3-pinctrl" }, |
||||
{ /* sentinel */ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(uniphier_sld3_pinctrl) = { |
||||
.name = "uniphier-sld3-pinctrl", |
||||
.id = UCLASS_PINCTRL, |
||||
.of_match = of_match_ptr(uniphier_sld3_pinctrl_match), |
||||
.probe = uniphier_sld3_pinctrl_probe, |
||||
.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), |
||||
.ops = &uniphier_pinctrl_ops, |
||||
}; |
||||
Loading…
Reference in new issue