This is not used in U-Boot. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
7 years ago
committed by
Tom Rini
parent
93d66ee566
commit
00aff7bbc3
@ -1,106 +0,0 @@ |
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/*
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* (C) Copyright 2009 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __MANROLAND_COMMON_H |
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#define __MANROLAND_COMMON_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_BOARD_EARLY_INIT_R |
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/*
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* Command line configuration. |
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*/ |
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#define CONFIG_CMD_DATE |
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#define CONFIG_CMD_EEPROM |
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#define CONFIG_CMD_DTT |
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#define CONFIG_CMD_IDE |
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/*
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* 8-symbol LED display (can be accessed with 'display' command) |
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*/ |
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#define CONFIG_PDSP188x |
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#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ |
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/*
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* Autobooting |
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*/ |
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#define CONFIG_PREBOOT "echo;" \ |
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo" |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addwdt=setenv bootargs ${bootargs} wdt=off\0" \
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"logval=4\0" \
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"addlog=setenv bootargs ${bootargs} loglevel=${logval}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"kernel_addr=ff810000\0" \
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"fdt_addr="__stringify(CONFIG_SYS_FLASH_BASE)"\0" \
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"flash_nfs=run nfsargs addip addcon addwdt addlog;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"kernel_addr_r=300000\0" \
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"fdt_addr_r=200000\0" \
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"fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
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__stringify(CONFIG_HOSTNAME) ".dtb\0" \
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"kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
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"load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
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"load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
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"addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\
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"net_nfs=run load_fdt load_kernel; " \
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"run nfsargs addip addcon addwdt addlog;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin \0" \
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"u-boot_addr_r=200000\0" \
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"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
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"update=protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
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"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_TEXT_BASE) \
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" ${filesize};" \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize}\0"\
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"" |
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#define CONFIG_BOOTCOMMAND "run net_nfs" |
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#define CONFIG_MISC_INIT_R 1 |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
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/* Enable an alternate, more extensive memory test */ |
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#define CONFIG_SYS_ALT_MEMTEST |
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/*
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* Enable loopw command. |
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*/ |
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#endif /* __MANROLAND_COMMON_H */ |
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@ -1,205 +0,0 @@ |
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/*
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* (C) Copyright 2009 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __MANROLAND_MPC52XX__COMMON_H |
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#define __MANROLAND_MPC52XX__COMMON_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC5200 1 /* MPC5200 CPU */ |
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
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/*
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* Serial console configuration |
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*/ |
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\ |
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230400 } |
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#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */ |
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# define CONFIG_SYS_LOWBOOT 1 |
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#endif |
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/*
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* IPB Bus clocking configuration. |
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*/ |
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
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/*
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* I2C configuration |
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*/ |
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
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#define CONFIG_SYS_I2C_SLAVE 0x7F |
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/*
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* EEPROM configuration |
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*/ |
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
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/*
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* RTC configuration |
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*/ |
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#define CONFIG_RTC_PCF8563 |
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
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/* I2C SYSMON (LM75) */ |
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#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ |
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
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#define CONFIG_SYS_DTT_MAX_TEMP 70 |
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#define CONFIG_SYS_DTT_LOW_TEMP -30 |
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#define CONFIG_SYS_DTT_HYSTERESIS 3 |
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/*
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* Flash configuration |
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*/ |
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#define CONFIG_SYS_FLASH_BASE 0xFF800000 |
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#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks |
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(= chip selects) */ |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/ |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_EMPTY_INFO |
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET |
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/*
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* Environment settings |
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*/ |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_ENV_SIZE 0x4000 |
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
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/*
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* Memory map |
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*/ |
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#define CONFIG_SYS_MBAR 0xF0000000 |
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ |
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GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ |
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#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ |
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/* Settings for XLB = 132 MHz */ |
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#define SDRAM_DDR 1 |
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#define SDRAM_MODE 0x018D0000 |
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#define SDRAM_EMODE 0x40090000 |
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#define SDRAM_CONTROL 0x714f0f00 |
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#define SDRAM_CONFIG1 0x73722930 |
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#define SDRAM_CONFIG2 0x47770000 |
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#define SDRAM_TAPDELAY 0x10000000 |
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/* Use ON-Chip SRAM until RAM will be available */ |
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
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#ifdef CONFIG_POST |
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/* preserve space for the post_word at end of on-chip SRAM */ |
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
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#else |
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
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#endif |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
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# define CONFIG_SYS_RAMBOOT 1 |
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#endif |
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) |
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#define CONFIG_SYS_MALLOC_LEN (512 << 10) |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
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/*
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* Ethernet configuration |
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*/ |
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#define CONFIG_MPC5xxx_FEC 1 |
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#define CONFIG_MPC5xxx_FEC_MII100 |
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#define CONFIG_PHY_ADDR 0x00 |
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#define CONFIG_MII 1 |
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/*use Hardware WDT */ |
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#define CONFIG_HW_WATCHDOG |
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
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#if defined(CONFIG_CMD_KGDB) |
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ |
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#endif |
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/*
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* Various low-level settings |
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*/ |
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
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#define CONFIG_SYS_HID0_FINAL HID0_ICE |
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE |
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE |
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/* 8Mbit SRAM @0x80100000 */ |
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#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE |
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#define CONFIG_SYS_CS_BURST 0x00000000 |
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 |
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk |
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*----------------------------------------------------------------------- |
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*/ |
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
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#undef CONFIG_IDE_LED /* LED for ide not supported */ |
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
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#define CONFIG_IDE_PREINIT 1 |
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
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/* Offset for data I/O */ |
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
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/* Offset for normal register accesses */ |
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
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/* Offset for alternate registers */ |
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
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/* Interval between registers */ |
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#define CONFIG_SYS_ATA_STRIDE 4 |
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#define CONFIG_ATAPI 1 |
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#define OF_CPU "PowerPC,5200@0" |
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#define OF_SOC "soc5200@f0000000" |
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#define OF_TBCLK (bd->bi_busfreq / 4) |
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#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
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#define CONFIG_OF_IDE_FIXUP |
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#endif /* __MANROLAND_MPC52XX__COMMON_H */ |
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