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@ -5,6 +5,9 @@ |
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* (C) Copyright 2015 |
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* Kamil Lulko, <rev13@wp.pl> |
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* |
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* Copyright 2015 ATS Advanced Telematics Systems GmbH |
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* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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@ -16,6 +19,7 @@ |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_STM32F4) |
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#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) |
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#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) |
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#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) |
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@ -82,6 +86,92 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, |
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out: |
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return rv; |
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} |
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#elif defined(CONFIG_STM32F1) |
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#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) |
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#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) |
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#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) |
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#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) |
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#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) |
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#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) |
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#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) |
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static const unsigned long io_base[] = { |
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STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, |
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STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, |
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STM32_GPIOG_BASE |
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}; |
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#define STM32_GPIO_CR_MODE_MASK 0x3 |
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#define STM32_GPIO_CR_MODE_SHIFT(p) (p * 4) |
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#define STM32_GPIO_CR_CNF_MASK 0x3 |
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#define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2) |
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struct stm32_gpio_regs { |
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u32 crl; /* GPIO port configuration low */ |
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u32 crh; /* GPIO port configuration high */ |
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u32 idr; /* GPIO port input data */ |
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u32 odr; /* GPIO port output data */ |
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u32 bsrr; /* GPIO port bit set/reset */ |
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u32 brr; /* GPIO port bit reset */ |
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u32 lckr; /* GPIO port configuration lock */ |
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}; |
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#define CHECK_DSC(x) (!x || x->port > 6 || x->pin > 15) |
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#define CHECK_CTL(x) (!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \ |
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x->pupd > 1) |
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int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, |
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const struct stm32_gpio_ctl *ctl) |
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{ |
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struct stm32_gpio_regs *gpio_regs; |
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u32 *cr; |
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int p, crp; |
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int rv; |
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if (CHECK_DSC(dsc)) { |
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rv = -EINVAL; |
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goto out; |
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} |
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if (CHECK_CTL(ctl)) { |
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rv = -EINVAL; |
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goto out; |
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} |
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p = dsc->pin; |
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gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; |
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/* Enable clock for GPIO port */ |
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setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port); |
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if (p < 8) { |
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cr = &gpio_regs->crl; |
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crp = p; |
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} else { |
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cr = &gpio_regs->crh; |
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crp = p - 8; |
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} |
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clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp)); |
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setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp)); |
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clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp)); |
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/* Inputs set the optional pull up / pull down */ |
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if (ctl->mode == STM32_GPIO_MODE_IN) { |
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setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp)); |
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clrbits_le32(&gpio_regs->odr, 0x1 << p); |
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setbits_le32(&gpio_regs->odr, ctl->pupd << p); |
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} else { |
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setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp)); |
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} |
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rv = 0; |
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out: |
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return rv; |
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} |
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#else |
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#error STM32 family not supported |
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#endif |
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int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state) |
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{ |
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@ -140,10 +230,20 @@ int gpio_direction_input(unsigned gpio) |
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dsc.port = stm32_gpio_to_port(gpio); |
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dsc.pin = stm32_gpio_to_pin(gpio); |
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#if defined(CONFIG_STM32F4) |
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ctl.af = STM32_GPIO_AF0; |
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ctl.mode = STM32_GPIO_MODE_IN; |
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ctl.otype = STM32_GPIO_OTYPE_PP; |
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ctl.pupd = STM32_GPIO_PUPD_NO; |
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ctl.speed = STM32_GPIO_SPEED_50M; |
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#elif defined(CONFIG_STM32F1) |
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ctl.mode = STM32_GPIO_MODE_IN; |
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ctl.icnf = STM32_GPIO_ICNF_IN_FLT; |
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ctl.ocnf = STM32_GPIO_OCNF_GP_PP; /* ignored for input */ |
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ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for floating */ |
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#else |
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#error STM32 family not supported |
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#endif |
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return stm32_gpio_config(&dsc, &ctl); |
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} |
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@ -156,11 +256,19 @@ int gpio_direction_output(unsigned gpio, int value) |
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dsc.port = stm32_gpio_to_port(gpio); |
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dsc.pin = stm32_gpio_to_pin(gpio); |
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#if defined(CONFIG_STM32F4) |
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ctl.af = STM32_GPIO_AF0; |
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ctl.mode = STM32_GPIO_MODE_OUT; |
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ctl.otype = STM32_GPIO_OTYPE_PP; |
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ctl.pupd = STM32_GPIO_PUPD_NO; |
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ctl.speed = STM32_GPIO_SPEED_50M; |
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#elif defined(CONFIG_STM32F1) |
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ctl.mode = STM32_GPIO_MODE_OUT_50M; |
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ctl.ocnf = STM32_GPIO_OCNF_GP_PP; |
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ctl.icnf = STM32_GPIO_ICNF_IN_FLT; /* ignored for output */ |
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ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for output */ |
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#else |
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#error STM32 family not supported |
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#endif |
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res = stm32_gpio_config(&dsc, &ctl); |
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if (res < 0) |
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