@ -50,4 +50,42 @@ struct stm32_rcc_clk {
enum soc_family soc ;
} ;
struct stm32_rcc_regs {
u32 cr ; /* RCC clock control */
u32 pllcfgr ; /* RCC PLL configuration */
u32 cfgr ; /* RCC clock configuration */
u32 cir ; /* RCC clock interrupt */
u32 ahb1rstr ; /* RCC AHB1 peripheral reset */
u32 ahb2rstr ; /* RCC AHB2 peripheral reset */
u32 ahb3rstr ; /* RCC AHB3 peripheral reset */
u32 rsv0 ;
u32 apb1rstr ; /* RCC APB1 peripheral reset */
u32 apb2rstr ; /* RCC APB2 peripheral reset */
u32 rsv1 [ 2 ] ;
u32 ahb1enr ; /* RCC AHB1 peripheral clock enable */
u32 ahb2enr ; /* RCC AHB2 peripheral clock enable */
u32 ahb3enr ; /* RCC AHB3 peripheral clock enable */
u32 rsv2 ;
u32 apb1enr ; /* RCC APB1 peripheral clock enable */
u32 apb2enr ; /* RCC APB2 peripheral clock enable */
u32 rsv3 [ 2 ] ;
u32 ahb1lpenr ; /* RCC AHB1 periph clk enable in low pwr mode */
u32 ahb2lpenr ; /* RCC AHB2 periph clk enable in low pwr mode */
u32 ahb3lpenr ; /* RCC AHB3 periph clk enable in low pwr mode */
u32 rsv4 ;
u32 apb1lpenr ; /* RCC APB1 periph clk enable in low pwr mode */
u32 apb2lpenr ; /* RCC APB2 periph clk enable in low pwr mode */
u32 rsv5 [ 2 ] ;
u32 bdcr ; /* RCC Backup domain control */
u32 csr ; /* RCC clock control & status */
u32 rsv6 [ 2 ] ;
u32 sscgr ; /* RCC spread spectrum clock generation */
u32 plli2scfgr ; /* RCC PLLI2S configuration */
/* below registers are only available on STM32F46x and STM32F7 SoCs*/
u32 pllsaicfgr ; /* PLLSAI configuration */
u32 dckcfgr ; /* dedicated clocks configuration register */
/* Below registers are only available on STM32F7 SoCs */
u32 dckcfgr2 ; /* dedicated clocks configuration register */
} ;
# endif /* __STM32_RCC_H_ */