ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)

This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(2) This patch renames the functions from 440spe_ to 4xx_ with a
    little additional cleanup

Signed-off-by: Stefan Roese <sr@denx.de>

board/amcc/katmai/katmai.c

@@ -35,9 +35,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int ppc440spe_init_pcie_rootport(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
-
 int board_early_init_f (void)
 {
 	unsigned long mfr;
@@ -409,9 +406,9 @@ void pcie_setup_hoses(int busno)
 			continue;
 
 #ifdef PCIE_ENDPOINT
- 		if (ppc440spe_init_pcie_endport(i)) {
+ 		if (ppc4xx_init_pcie_endport(i)) {
 #else
-		if (ppc440spe_init_pcie_rootport(i)) {
+		if (ppc4xx_init_pcie_rootport(i)) {
 #endif
 			printf("PCIE%d: initialization failed\n", i);
 			continue;
@@ -433,13 +430,13 @@ void pcie_setup_hoses(int busno)
 		pci_register_hose(hose);
 
 #ifdef PCIE_ENDPOINT
-		ppc440spe_setup_pcie_endpoint(hose, i);
+		ppc4xx_setup_pcie_endpoint(hose, i);
 		/*
 		 * Reson for no scanning is endpoint can not generate
 		 * upstream configuration accesses.
 		 */
 #else
-		ppc440spe_setup_pcie_rootpoint(hose, i);
+		ppc4xx_setup_pcie_rootpoint(hose, i);
 
 		env = getenv ("pciscandelay");
 		if (env != NULL) {

board/amcc/yucca/yucca.c

@@ -47,9 +47,6 @@ char *remove_l_w_space(char *in_str );
 char *remove_t_w_space(char *in_str );
 int get_console_port(void);
 
-int ppc440spe_init_pcie_rootport(int port);
-void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
-
 #define DEBUG_ENV
 #ifdef DEBUG_ENV
 #define DEBUGF(fmt,args...) printf(fmt ,##args)
@@ -865,10 +862,10 @@ void pcie_setup_hoses(int busno)
 
 #ifdef PCIE_ENDPOINT
  		yucca_setup_pcie_fpga_endpoint(i);
- 		if (ppc440spe_init_pcie_endport(i)) {
+ 		if (ppc4xx_init_pcie_endport(i)) {
 #else
 		yucca_setup_pcie_fpga_rootpoint(i);
-		if (ppc440spe_init_pcie_rootport(i)) {
+		if (ppc4xx_init_pcie_rootport(i)) {
 #endif
 			printf("PCIE%d: initialization failed\n", i);
 			continue;
@@ -890,13 +887,13 @@ void pcie_setup_hoses(int busno)
 		pci_register_hose(hose);
 
 #ifdef PCIE_ENDPOINT
-		ppc440spe_setup_pcie_endpoint(hose, i);
+		ppc4xx_setup_pcie_endpoint(hose, i);
 		/*
 		 * Reson for no scanning is endpoint can not generate
 		 * upstream configuration accesses.
 		 */
 #else
-		ppc440spe_setup_pcie_rootpoint(hose, i);
+		ppc4xx_setup_pcie_rootpoint(hose, i);
 
 		env = getenv ("pciscandelay");
 		if (env != NULL) {

cpu/ppc4xx/4xx_pcie.c

@@ -222,7 +222,7 @@ int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset
 	return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
 }
 
-static void ppc440spe_setup_utl(u32 port) {
+static void ppc4xx_setup_utl(u32 port) {
 
 	volatile void *utl_base = NULL;
 
@@ -333,7 +333,7 @@ static int check_error(void)
 /*
  * Initialize PCI Express core
  */
-int ppc440spe_init_pcie(void)
+int ppc4xx_init_pcie(void)
 {
 	int time_out = 20;
 
@@ -401,7 +401,7 @@ int ppc440spe_init_pcie(void)
  *  which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
  *  data at 0x9000 0000(SRAM).Data should match.
  */
-int ppc440spe_init_pcie_rootport(int port)
+int ppc4xx_init_pcie_rootport(int port)
 {
 	static int core_init;
 	volatile u32 val = 0;
@@ -409,7 +409,7 @@ int ppc440spe_init_pcie_rootport(int port)
 
 	if (!core_init) {
 		++core_init;
-		if (ppc440spe_init_pcie())
+		if (ppc4xx_init_pcie())
 			return -1;
 	}
 
@@ -520,7 +520,7 @@ int ppc440spe_init_pcie_rootport(int port)
 	 * We use default settings for revB chip.
 	 */
 	if (!ppc440spe_revB())
-		ppc440spe_setup_utl(port);
+		ppc4xx_setup_utl(port);
 
 	/*
 	 * We map PCI Express configuration access into the 512MB regions
@@ -620,7 +620,7 @@ int ppc440spe_init_pcie_rootport(int port)
 	return 0;
 }
 
-int ppc440spe_init_pcie_endport(int port)
+int ppc4xx_init_pcie_endport(int port)
 {
 	static int core_init;
 	volatile u32 val = 0;
@@ -628,7 +628,7 @@ int ppc440spe_init_pcie_endport(int port)
 
 	if (!core_init) {
 		++core_init;
-		if (ppc440spe_init_pcie())
+		if (ppc4xx_init_pcie())
 			return -1;
 	}
 
@@ -734,7 +734,7 @@ int ppc440spe_init_pcie_endport(int port)
 	 * We use default settings for revB chip.
 	 */
 	if (!ppc440spe_revB())
-		ppc440spe_setup_utl(port);
+		ppc4xx_setup_utl(port);
 
 	/*
 	 * We map PCI Express configuration access into the 512MB regions
@@ -833,7 +833,7 @@ int ppc440spe_init_pcie_endport(int port)
 	return 0;
 }
 
-void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
+void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 {
 	volatile void *mbase = NULL;
 	volatile void *rmbase = NULL;
@@ -951,7 +951,7 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 
 }
 
-int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
+int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 {
 	volatile void *mbase = NULL;
 	int attempts = 0;

include/asm-ppc/4xx_pcie.h

@@ -9,8 +9,8 @@
  */
 
 #include <ppc4xx.h>
-#ifndef __440SPE_PCIE_H
-#define __440SPE_PCIE_H
+#ifndef __4XX_PCIE_H
+#define __4XX_PCIE_H
 
 #define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);})
 
@@ -164,11 +164,10 @@
 
 #define GPL_DMER_MASK_DISA	0x02000000
 
-int ppc440spe_init_pcie(void);
-int ppc440spe_init_pcie_rootport(int port);
-void yucca_setup_pcie_fpga_rootpoint(int port);
-void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port);
-int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port);
-int yucca_pcie_card_present(int port);
+int ppc4xx_init_pcie(void);
+int ppc4xx_init_pcie_rootport(int port);
+void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
+int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
 int pcie_hose_scan(struct pci_controller *hose, int bus);
-#endif /* __440SPE_PCIE_H */
+
+#endif /* __4XX_PCIE_H */