Fix a trivial conflict in dw_mmc.c after talking with Marek. Conflicts: drivers/mmc/dw_mmc.c Signed-off-by: Tom Rini <trini@ti.com>master
Tom Rini
11 years ago
commit
04de09f89b
@ -0,0 +1,78 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* This file contains only support functions used also by the SoCFPGA |
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* platform code, the real meat is located in drivers/fpga/socfpga.c . |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/fpga_manager.h> |
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#include <asm/arch/reset_manager.h> |
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#include <asm/arch/system_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Timeout count */ |
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#define FPGA_TIMEOUT_CNT 0x1000000 |
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static struct socfpga_fpga_manager *fpgamgr_regs = |
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(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
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/* Check whether FPGA Init_Done signal is high */ |
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static int is_fpgamgr_initdone_high(void) |
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{ |
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unsigned long val; |
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val = readl(&fpgamgr_regs->gpio_ext_porta); |
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return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK; |
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} |
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/* Get the FPGA mode */ |
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int fpgamgr_get_mode(void) |
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{ |
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unsigned long val; |
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val = readl(&fpgamgr_regs->stat); |
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return val & FPGAMGRREGS_STAT_MODE_MASK; |
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} |
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/* Check whether FPGA is ready to be accessed */ |
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int fpgamgr_test_fpga_ready(void) |
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{ |
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/* Check for init done signal */ |
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if (!is_fpgamgr_initdone_high()) |
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return 0; |
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/* Check again to avoid false glitches */ |
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if (!is_fpgamgr_initdone_high()) |
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return 0; |
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE) |
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return 0; |
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return 1; |
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} |
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/* Poll until FPGA is ready to be accessed or timeout occurred */ |
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int fpgamgr_poll_fpga_ready(void) |
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{ |
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unsigned long i; |
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/* If FPGA is blank, wait till WD invoke warm reset */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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/* check for init done signal */ |
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if (!is_fpgamgr_initdone_high()) |
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continue; |
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/* check again to avoid false glitches */ |
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if (!is_fpgamgr_initdone_high()) |
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continue; |
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return 1; |
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} |
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return 0; |
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} |
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@ -0,0 +1,77 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef _FPGA_MANAGER_H_ |
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#define _FPGA_MANAGER_H_ |
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#include <altera.h> |
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struct socfpga_fpga_manager { |
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/* FPGA Manager Module */ |
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u32 stat; /* 0x00 */ |
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u32 ctrl; |
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u32 dclkcnt; |
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u32 dclkstat; |
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u32 gpo; /* 0x10 */ |
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u32 gpi; |
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u32 misci; /* 0x18 */ |
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u32 _pad_0x1c_0x82c[517]; |
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|
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/* Configuration Monitor (MON) Registers */ |
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u32 gpio_inten; /* 0x830 */ |
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u32 gpio_intmask; |
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u32 gpio_inttype_level; |
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u32 gpio_int_polarity; |
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u32 gpio_intstatus; /* 0x840 */ |
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u32 gpio_raw_intstatus; |
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u32 _pad_0x848; |
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u32 gpio_porta_eoi; |
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u32 gpio_ext_porta; /* 0x850 */ |
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u32 _pad_0x854_0x85c[3]; |
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u32 gpio_1s_sync; /* 0x860 */ |
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u32 _pad_0x864_0x868[2]; |
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u32 gpio_ver_id_code; |
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u32 gpio_config_reg2; /* 0x870 */ |
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u32 gpio_config_reg1; |
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}; |
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#define FPGAMGRREGS_STAT_MODE_MASK 0x7 |
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#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 |
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#define FPGAMGRREGS_STAT_MSEL_LSB 3 |
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#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 |
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#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 |
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#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 |
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#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 |
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#define FPGAMGRREGS_CTRL_EN_MASK 0x1 |
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#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 |
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/* FPGA Mode */ |
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#define FPGAMGRREGS_MODE_FPGAOFF 0x0 |
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#define FPGAMGRREGS_MODE_RESETPHASE 0x1 |
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#define FPGAMGRREGS_MODE_CFGPHASE 0x2 |
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#define FPGAMGRREGS_MODE_INITPHASE 0x3 |
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#define FPGAMGRREGS_MODE_USERMODE 0x4 |
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#define FPGAMGRREGS_MODE_UNKNOWN 0x5 |
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/* FPGA CD Ratio Value */ |
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#define CDRATIO_x1 0x0 |
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#define CDRATIO_x2 0x1 |
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#define CDRATIO_x4 0x2 |
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#define CDRATIO_x8 0x3 |
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/* SoCFPGA support functions */ |
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int fpgamgr_test_fpga_ready(void); |
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int fpgamgr_poll_fpga_ready(void); |
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int fpgamgr_get_mode(void); |
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#endif /* _FPGA_MANAGER_H_ */ |
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@ -0,0 +1,195 @@ |
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/*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _NIC301_REGISTERS_H_ |
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#define _NIC301_REGISTERS_H_ |
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struct nic301_registers { |
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u32 remap; /* 0x0 */ |
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/* Security Register Group */ |
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u32 _pad_0x4_0x8[1]; |
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u32 l4main; |
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u32 l4sp; |
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u32 l4mp; /* 0x10 */ |
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u32 l4osc1; |
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u32 l4spim; |
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u32 stm; |
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u32 lwhps2fpgaregs; /* 0x20 */ |
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u32 _pad_0x24_0x28[1]; |
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u32 usb1; |
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u32 nanddata; |
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u32 _pad_0x30_0x80[20]; |
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u32 usb0; /* 0x80 */ |
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u32 nandregs; |
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u32 qspidata; |
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u32 fpgamgrdata; |
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u32 hps2fpgaregs; /* 0x90 */ |
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u32 acp; |
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u32 rom; |
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u32 ocram; |
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u32 sdrdata; /* 0xA0 */ |
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u32 _pad_0xa4_0x1fd0[1995]; |
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/* ID Register Group */ |
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u32 periph_id_4; /* 0x1FD0 */ |
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u32 _pad_0x1fd4_0x1fe0[3]; |
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u32 periph_id_0; /* 0x1FE0 */ |
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u32 periph_id_1; |
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u32 periph_id_2; |
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u32 periph_id_3; |
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u32 comp_id_0; /* 0x1FF0 */ |
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u32 comp_id_1; |
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u32 comp_id_2; |
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u32 comp_id_3; |
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u32 _pad_0x2000_0x2008[2]; |
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/* L4 MAIN */ |
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u32 l4main_fn_mod_bm_iss; |
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u32 _pad_0x200c_0x3008[1023]; |
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/* L4 SP */ |
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u32 l4sp_fn_mod_bm_iss; |
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u32 _pad_0x300c_0x4008[1023]; |
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/* L4 MP */ |
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u32 l4mp_fn_mod_bm_iss; |
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u32 _pad_0x400c_0x5008[1023]; |
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/* L4 OSC1 */ |
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u32 l4osc_fn_mod_bm_iss; |
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u32 _pad_0x500c_0x6008[1023]; |
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/* L4 SPIM */ |
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u32 l4spim_fn_mod_bm_iss; |
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u32 _pad_0x600c_0x7008[1023]; |
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/* STM */ |
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u32 stm_fn_mod_bm_iss; |
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u32 _pad_0x700c_0x7108[63]; |
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u32 stm_fn_mod; |
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u32 _pad_0x710c_0x8008[959]; |
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/* LWHPS2FPGA */ |
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u32 lwhps2fpga_fn_mod_bm_iss; |
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u32 _pad_0x800c_0x8108[63]; |
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u32 lwhps2fpga_fn_mod; |
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u32 _pad_0x810c_0xa008[1983]; |
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/* USB1 */ |
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u32 usb1_fn_mod_bm_iss; |
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u32 _pad_0xa00c_0xa044[14]; |
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u32 usb1_ahb_cntl; |
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u32 _pad_0xa048_0xb008[1008]; |
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/* NANDDATA */ |
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u32 nanddata_fn_mod_bm_iss; |
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u32 _pad_0xb00c_0xb108[63]; |
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u32 nanddata_fn_mod; |
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u32 _pad_0xb10c_0x20008[21439]; |
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/* USB0 */ |
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u32 usb0_fn_mod_bm_iss; |
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u32 _pad_0x2000c_0x20044[14]; |
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u32 usb0_ahb_cntl; |
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u32 _pad_0x20048_0x21008[1008]; |
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/* NANDREGS */ |
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u32 nandregs_fn_mod_bm_iss; |
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u32 _pad_0x2100c_0x21108[63]; |
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u32 nandregs_fn_mod; |
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u32 _pad_0x2110c_0x22008[959]; |
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/* QSPIDATA */ |
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u32 qspidata_fn_mod_bm_iss; |
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u32 _pad_0x2200c_0x22044[14]; |
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u32 qspidata_ahb_cntl; |
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u32 _pad_0x22048_0x23008[1008]; |
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/* FPGAMGRDATA */ |
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u32 fpgamgrdata_fn_mod_bm_iss; |
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u32 _pad_0x2300c_0x23040[13]; |
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u32 fpgamgrdata_wr_tidemark; /* 0x23040 */ |
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u32 _pad_0x23044_0x23108[49]; |
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u32 fn_mod; |
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u32 _pad_0x2310c_0x24008[959]; |
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/* HPS2FPGA */ |
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u32 hps2fpga_fn_mod_bm_iss; |
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u32 _pad_0x2400c_0x24040[13]; |
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u32 hps2fpga_wr_tidemark; /* 0x24040 */ |
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u32 _pad_0x24044_0x24108[49]; |
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u32 hps2fpga_fn_mod; |
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u32 _pad_0x2410c_0x25008[959]; |
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/* ACP */ |
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u32 acp_fn_mod_bm_iss; |
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u32 _pad_0x2500c_0x25108[63]; |
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u32 acp_fn_mod; |
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u32 _pad_0x2510c_0x26008[959]; |
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/* Boot ROM */ |
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u32 bootrom_fn_mod_bm_iss; |
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u32 _pad_0x2600c_0x26108[63]; |
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u32 bootrom_fn_mod; |
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u32 _pad_0x2610c_0x27008[959]; |
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/* On-chip RAM */ |
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u32 ocram_fn_mod_bm_iss; |
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u32 _pad_0x2700c_0x27040[13]; |
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u32 ocram_wr_tidemark; /* 0x27040 */ |
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u32 _pad_0x27044_0x27108[49]; |
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u32 ocram_fn_mod; |
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u32 _pad_0x2710c_0x42024[27590]; |
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/* DAP */ |
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u32 dap_fn_mod2; |
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u32 dap_fn_mod_ahb; |
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u32 _pad_0x4202c_0x42100[53]; |
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u32 dap_read_qos; /* 0x42100 */ |
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u32 dap_write_qos; |
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u32 dap_fn_mod; |
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u32 _pad_0x4210c_0x43100[1021]; |
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/* MPU */ |
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u32 mpu_read_qos; /* 0x43100 */ |
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u32 mpu_write_qos; |
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u32 mpu_fn_mod; |
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u32 _pad_0x4310c_0x44028[967]; |
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/* SDMMC */ |
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u32 sdmmc_fn_mod_ahb; |
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u32 _pad_0x4402c_0x44100[53]; |
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u32 sdmmc_read_qos; /* 0x44100 */ |
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u32 sdmmc_write_qos; |
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u32 sdmmc_fn_mod; |
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u32 _pad_0x4410c_0x45100[1021]; |
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/* DMA */ |
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u32 dma_read_qos; /* 0x45100 */ |
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u32 dma_write_qos; |
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u32 dma_fn_mod; |
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u32 _pad_0x4510c_0x46040[973]; |
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/* FPGA2HPS */ |
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u32 fpga2hps_wr_tidemark; /* 0x46040 */ |
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u32 _pad_0x46044_0x46100[47]; |
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u32 fpga2hps_read_qos; /* 0x46100 */ |
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u32 fpga2hps_write_qos; |
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u32 fpga2hps_fn_mod; |
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u32 _pad_0x4610c_0x47100[1021]; |
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/* ETR */ |
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u32 etr_read_qos; /* 0x47100 */ |
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u32 etr_write_qos; |
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u32 etr_fn_mod; |
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u32 _pad_0x4710c_0x48100[1021]; |
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/* EMAC0 */ |
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u32 emac0_read_qos; /* 0x48100 */ |
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u32 emac0_write_qos; |
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u32 emac0_fn_mod; |
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u32 _pad_0x4810c_0x49100[1021]; |
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/* EMAC1 */ |
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u32 emac1_read_qos; /* 0x49100 */ |
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u32 emac1_write_qos; |
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u32 emac1_fn_mod; |
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u32 _pad_0x4910c_0x4a028[967]; |
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/* USB0 */ |
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u32 usb0_fn_mod_ahb; |
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u32 _pad_0x4a02c_0x4a100[53]; |
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u32 usb0_read_qos; /* 0x4A100 */ |
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u32 usb0_write_qos; |
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u32 usb0_fn_mod; |
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u32 _pad_0x4a10c_0x4b100[1021]; |
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/* NAND */ |
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u32 nand_read_qos; /* 0x4B100 */ |
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u32 nand_write_qos; |
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u32 nand_fn_mod; |
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u32 _pad_0x4b10c_0x4c028[967]; |
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/* USB1 */ |
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u32 usb1_fn_mod_ahb; |
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u32 _pad_0x4c02c_0x4c100[53]; |
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u32 usb1_read_qos; /* 0x4C100 */ |
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u32 usb1_write_qos; |
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u32 usb1_fn_mod; |
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}; |
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#endif /* _NIC301_REGISTERS_H_ */ |
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@ -0,0 +1,23 @@ |
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/*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __SOCFPGA_SCU_H__ |
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#define __SOCFPGA_SCU_H__ |
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struct scu_registers { |
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u32 ctrl; /* 0x00 */ |
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u32 cfg; |
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u32 cpsr; |
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u32 iassr; |
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u32 _pad_0x10_0x3c[12]; /* 0x10 */ |
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u32 fsar; /* 0x40 */ |
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u32 fear; |
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u32 _pad_0x48_0x50[2]; |
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u32 acr; /* 0x54 */ |
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u32 sacr; |
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}; |
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#endif /* __SOCFPGA_SCU_H__ */ |
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@ -0,0 +1,301 @@ |
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/fpga_manager.h> |
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#include <asm/arch/reset_manager.h> |
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#include <asm/arch/system_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Timeout count */ |
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#define FPGA_TIMEOUT_CNT 0x1000000 |
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static struct socfpga_fpga_manager *fpgamgr_regs = |
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(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
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static struct socfpga_system_manager *sysmgr_regs = |
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
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|
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/* Set CD ratio */ |
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static void fpgamgr_set_cd_ratio(unsigned long ratio) |
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{ |
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clrsetbits_le32(&fpgamgr_regs->ctrl, |
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0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, |
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(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); |
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} |
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static int fpgamgr_dclkcnt_set(unsigned long cnt) |
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{ |
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unsigned long i; |
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|
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/* Clear any existing done status */ |
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if (readl(&fpgamgr_regs->dclkstat)) |
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writel(0x1, &fpgamgr_regs->dclkstat); |
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|
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/* Write the dclkcnt */ |
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writel(cnt, &fpgamgr_regs->dclkcnt); |
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|
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/* Wait till the dclkcnt done */ |
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
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if (!readl(&fpgamgr_regs->dclkstat)) |
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continue; |
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writel(0x1, &fpgamgr_regs->dclkstat); |
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return 0; |
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} |
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return -ETIMEDOUT; |
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} |
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|
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/* Start the FPGA programming by initialize the FPGA Manager */ |
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static int fpgamgr_program_init(void) |
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{ |
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unsigned long msel, i; |
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|
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/* Get the MSEL value */ |
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msel = readl(&fpgamgr_regs->stat); |
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msel &= FPGAMGRREGS_STAT_MSEL_MASK; |
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msel >>= FPGAMGRREGS_STAT_MSEL_LSB; |
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|
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/*
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* Set the cfg width |
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* If MSEL[3] = 1, cfg width = 32 bit |
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*/ |
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if (msel & 0x8) { |
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setbits_le32(&fpgamgr_regs->ctrl, |
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FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
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|
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/* To determine the CD ratio */ |
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/* MSEL[1:0] = 0, CD Ratio = 1 */ |
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if ((msel & 0x3) == 0x0) |
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fpgamgr_set_cd_ratio(CDRATIO_x1); |
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/* MSEL[1:0] = 1, CD Ratio = 4 */ |
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else if ((msel & 0x3) == 0x1) |
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fpgamgr_set_cd_ratio(CDRATIO_x4); |
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/* MSEL[1:0] = 2, CD Ratio = 8 */ |
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else if ((msel & 0x3) == 0x2) |
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fpgamgr_set_cd_ratio(CDRATIO_x8); |
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} else { /* MSEL[3] = 0 */ |
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clrbits_le32(&fpgamgr_regs->ctrl, |
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FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
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|
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/* To determine the CD ratio */ |
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/* MSEL[1:0] = 0, CD Ratio = 1 */ |
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if ((msel & 0x3) == 0x0) |
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fpgamgr_set_cd_ratio(CDRATIO_x1); |
||||
/* MSEL[1:0] = 1, CD Ratio = 2 */ |
||||
else if ((msel & 0x3) == 0x1) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x2); |
||||
/* MSEL[1:0] = 2, CD Ratio = 4 */ |
||||
else if ((msel & 0x3) == 0x2) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x4); |
||||
} |
||||
|
||||
/* To enable FPGA Manager configuration */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); |
||||
|
||||
/* To enable FPGA Manager drive over configuration line */ |
||||
setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
||||
|
||||
/* Put FPGA into reset phase */ |
||||
setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
||||
|
||||
/* (1) wait until FPGA enter reset phase */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) |
||||
break; |
||||
} |
||||
|
||||
/* If not in reset state, return error */ |
||||
if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { |
||||
puts("FPGA: Could not reset\n"); |
||||
return -1; |
||||
} |
||||
|
||||
/* Release FPGA from reset phase */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
||||
|
||||
/* (2) wait until FPGA enter configuration phase */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) |
||||
break; |
||||
} |
||||
|
||||
/* If not in configuration state, return error */ |
||||
if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { |
||||
puts("FPGA: Could not configure\n"); |
||||
return -2; |
||||
} |
||||
|
||||
/* Clear all interrupts in CB Monitor */ |
||||
writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); |
||||
|
||||
/* Enable AXI configuration */ |
||||
setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Write the RBF data to FPGA Manager */ |
||||
static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size) |
||||
{ |
||||
uint32_t src = (uint32_t)rbf_data; |
||||
uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS; |
||||
|
||||
/* Number of loops for 32-byte long copying. */ |
||||
uint32_t loops32 = rbf_size / 32; |
||||
/* Number of loops for 4-byte long copying + trailing bytes */ |
||||
uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); |
||||
|
||||
asm volatile( |
||||
"1: ldmia %0!, {r0-r7}\n" |
||||
" stmia %1!, {r0-r7}\n" |
||||
" sub %1, #32\n" |
||||
" subs %2, #1\n" |
||||
" bne 1b\n" |
||||
"2: ldr %2, [%0], #4\n" |
||||
" str %2, [%1]\n" |
||||
" subs %3, #1\n" |
||||
" bne 2b\n" |
||||
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : |
||||
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); |
||||
} |
||||
|
||||
/* Ensure the FPGA entering config done */ |
||||
static int fpgamgr_program_poll_cd(void) |
||||
{ |
||||
const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | |
||||
FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; |
||||
unsigned long reg, i; |
||||
|
||||
/* (3) wait until full config done */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
reg = readl(&fpgamgr_regs->gpio_ext_porta); |
||||
|
||||
/* Config error */ |
||||
if (!(reg & mask)) { |
||||
printf("FPGA: Configuration error.\n"); |
||||
return -3; |
||||
} |
||||
|
||||
/* Config done without error */ |
||||
if (reg & mask) |
||||
break; |
||||
} |
||||
|
||||
/* Timeout happened, return error */ |
||||
if (i == FPGA_TIMEOUT_CNT) { |
||||
printf("FPGA: Timeout waiting for program.\n"); |
||||
return -4; |
||||
} |
||||
|
||||
/* Disable AXI configuration */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ensure the FPGA entering init phase */ |
||||
static int fpgamgr_program_poll_initphase(void) |
||||
{ |
||||
unsigned long i; |
||||
|
||||
/* Additional clocks for the CB to enter initialization phase */ |
||||
if (fpgamgr_dclkcnt_set(0x4)) |
||||
return -5; |
||||
|
||||
/* (4) wait until FPGA enter init phase or user mode */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) |
||||
break; |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
||||
break; |
||||
} |
||||
|
||||
/* If not in configuration state, return error */ |
||||
if (i == FPGA_TIMEOUT_CNT) |
||||
return -6; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ensure the FPGA entering user mode */ |
||||
static int fpgamgr_program_poll_usermode(void) |
||||
{ |
||||
unsigned long i; |
||||
|
||||
/* Additional clocks for the CB to exit initialization phase */ |
||||
if (fpgamgr_dclkcnt_set(0x5000)) |
||||
return -7; |
||||
|
||||
/* (5) wait until FPGA enter user mode */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
||||
break; |
||||
} |
||||
/* If not in configuration state, return error */ |
||||
if (i == FPGA_TIMEOUT_CNT) |
||||
return -8; |
||||
|
||||
/* To release FPGA Manager drive over configuration line */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* FPGA Manager to program the FPGA. This is the interface used by FPGA driver. |
||||
* Return 0 for sucess, non-zero for error. |
||||
*/ |
||||
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) |
||||
{ |
||||
unsigned long status; |
||||
|
||||
if ((uint32_t)rbf_data & 0x3) { |
||||
puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/* Prior programming the FPGA, all bridges need to be shut off */ |
||||
|
||||
/* Disable all signals from hps peripheral controller to fpga */ |
||||
writel(0, &sysmgr_regs->fpgaintfgrp_module); |
||||
|
||||
/* Disable all signals from FPGA to HPS SDRAM */ |
||||
#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 |
||||
writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); |
||||
|
||||
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ |
||||
socfpga_bridges_reset(1); |
||||
|
||||
/* Unmap the bridges from NIC-301 */ |
||||
writel(0x1, SOCFPGA_L3REGS_ADDRESS); |
||||
|
||||
/* Initialize the FPGA Manager */ |
||||
status = fpgamgr_program_init(); |
||||
if (status) |
||||
return status; |
||||
|
||||
/* Write the RBF data to FPGA Manager */ |
||||
fpgamgr_program_write(rbf_data, rbf_size); |
||||
|
||||
/* Ensure the FPGA entering config done */ |
||||
status = fpgamgr_program_poll_cd(); |
||||
if (status) |
||||
return status; |
||||
|
||||
/* Ensure the FPGA entering init phase */ |
||||
status = fpgamgr_program_poll_initphase(); |
||||
if (status) |
||||
return status; |
||||
|
||||
/* Ensure the FPGA entering user mode */ |
||||
return fpgamgr_program_poll_usermode(); |
||||
} |
||||
@ -0,0 +1,196 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ |
||||
#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ |
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
|
||||
/* Virtual target or real hardware */ |
||||
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
|
||||
#define CONFIG_ARMV7 |
||||
#define CONFIG_SYS_THUMB_BUILD |
||||
|
||||
#define CONFIG_SOCFPGA |
||||
|
||||
/*
|
||||
* High level configuration |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_CLOCKS |
||||
|
||||
#define CONFIG_FIT |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
/*
|
||||
* Memory configurations |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM_1 0x0 |
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define CONFIG_SYS_TEXT_BASE 0x08000040 |
||||
#else |
||||
#define CONFIG_SYS_TEXT_BASE 0x01000040 |
||||
#endif |
||||
|
||||
/*
|
||||
* U-Boot general configurations |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
||||
#define CONFIG_SYS_PBSIZE \ |
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
/* Print buffer size */ |
||||
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
/* Boot argument buffer size */ |
||||
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ |
||||
#define CONFIG_AUTO_COMPLETE /* Command auto complete */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command history etc */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/*
|
||||
* Cache |
||||
*/ |
||||
#define CONFIG_SYS_ARM_CACHE_WRITEALLOC |
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 |
||||
#define CONFIG_SYS_L2_PL310 |
||||
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS |
||||
|
||||
/*
|
||||
* Ethernet on SoC (EMAC) |
||||
*/ |
||||
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) |
||||
#define CONFIG_DESIGNWARE_ETH |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_DW_ALTDESCRIPTOR |
||||
#define CONFIG_MII |
||||
#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_GIGE |
||||
#endif |
||||
|
||||
/*
|
||||
* FPGA Driver |
||||
*/ |
||||
#ifdef CONFIG_CMD_FPGA |
||||
#define CONFIG_FPGA |
||||
#define CONFIG_FPGA_ALTERA |
||||
#define CONFIG_FPGA_SOCFPGA |
||||
#define CONFIG_FPGA_COUNT 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* L4 OSC1 Timer 0 |
||||
*/ |
||||
/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ |
||||
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
||||
#define CONFIG_SYS_TIMER_COUNTS_DOWN |
||||
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) |
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define CONFIG_SYS_TIMER_RATE 2400000 |
||||
#else |
||||
#define CONFIG_SYS_TIMER_RATE 25000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* L4 Watchdog |
||||
*/ |
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
#define CONFIG_DESIGNWARE_WATCHDOG |
||||
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
||||
#define CONFIG_DW_WDT_CLOCK_KHZ 25000 |
||||
#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 |
||||
#endif |
||||
|
||||
/*
|
||||
* MMC Driver |
||||
*/ |
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_DWMMC |
||||
#define CONFIG_SOCFPGA_DWMMC |
||||
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 |
||||
#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 |
||||
#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 |
||||
/* FIXME */ |
||||
/* using smaller max blk cnt to avoid flooding the limited stack we have */ |
||||
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial Driver |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 |
||||
#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS |
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define CONFIG_SYS_NS16550_CLK 1000000 |
||||
#else |
||||
#define CONFIG_SYS_NS16550_CLK 100000000 |
||||
#endif |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* U-Boot environment |
||||
*/ |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
#define CONFIG_ENV_SIZE 4096 |
||||
|
||||
/*
|
||||
* SPL |
||||
*/ |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
#define CONFIG_SPL_BOARD_INIT |
||||
#define CONFIG_SPL_RAM_DEVICE |
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 |
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
||||
#define CONFIG_SPL_STACK_SIZE (4 * 1024) |
||||
#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */ |
||||
#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) |
||||
|
||||
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ |
||||
#define CONFIG_CRC32_VERIFY |
||||
|
||||
/* Linker script for SPL */ |
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" |
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_WATCHDOG_SUPPORT |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#undef CONFIG_PARTITIONS |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ |
||||
@ -1,287 +1,100 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com> |
||||
* Copyright (C) 2014 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ |
||||
#define __CONFIG_SOCFPGA_CYCLONE5_H__ |
||||
|
||||
#include <asm/arch/socfpga_base_addrs.h> |
||||
#include "../../board/altera/socfpga/pinmux_config.h" |
||||
#include "../../board/altera/socfpga/iocsr_config.h" |
||||
#include "../../board/altera/socfpga/pll_config.h" |
||||
|
||||
/*
|
||||
* High level configuration |
||||
*/ |
||||
/* Virtual target or real hardware */ |
||||
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
|
||||
#define CONFIG_ARMV7 |
||||
#define CONFIG_SYS_DCACHE_OFF |
||||
#undef CONFIG_USE_IRQ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_SINGLE_BOOTLOADER |
||||
#define CONFIG_SOCFPGA |
||||
|
||||
/* base address for .text section */ |
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define CONFIG_SYS_TEXT_BASE 0x08000040 |
||||
#else |
||||
#define CONFIG_SYS_TEXT_BASE 0x01000040 |
||||
#endif |
||||
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 |
||||
|
||||
/* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
/* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
|
||||
/*
|
||||
* Display CPU and Board Info |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
/*
|
||||
* Enable early stage initialization at C environment |
||||
*/ |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
/* flat device tree */ |
||||
#define CONFIG_OF_LIBFDT |
||||
/* skip updating the FDT blob */ |
||||
#define CONFIG_FDT_BLOB_SKIP_UPDATE |
||||
/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ |
||||
#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) |
||||
|
||||
#define CONFIG_SPL_RAM_DEVICE |
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
||||
#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) |
||||
|
||||
/*
|
||||
* Memory allocation (MALLOC) |
||||
*/ |
||||
/* Room required on the stack for the environment data */ |
||||
#define CONFIG_ENV_SIZE 1024 |
||||
/* Size of DRAM reserved for malloc() use */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
|
||||
/* SP location before relocation, must use scratch RAM */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
||||
/* Reserving 0x100 space at back of scratch RAM for debug info */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) |
||||
/* Stack pointer prior relocation, must situated at on-chip RAM */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
/* U-Boot Commands */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#include <config_cmd_default.h> |
||||
/* FAT file system support */ |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_FAT_WRITE |
||||
#define CONFIG_HW_WATCHDOG |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EXT4 |
||||
#define CONFIG_CMD_EXT4_WRITE |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_FPGA |
||||
#define CONFIG_CMD_FS_GENERIC |
||||
#define CONFIG_CMD_GREPENV |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#define CONFIG_REGEX /* Enable regular expression support */ |
||||
|
||||
/*
|
||||
* Misc |
||||
*/ |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
/* Memory configurations */ |
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#undef CONFIG_PARTITIONS |
||||
/* Booting Linux */ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTFILE "zImage" |
||||
#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) |
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define CONFIG_BOOTCOMMAND "run ramboot" |
||||
#else |
||||
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" |
||||
#endif |
||||
#define CONFIG_LOADADDR 0x8000 |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/*
|
||||
* Environment setup |
||||
*/ |
||||
/* Ethernet on SoC (EMAC) */ |
||||
#if defined(CONFIG_CMD_NET) |
||||
#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS |
||||
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
||||
#define CONFIG_EPHY0_PHY_ADDR 0 |
||||
|
||||
/* Delay before automatically booting the default image */ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
/* Enable auto completion of commands using TAB */ |
||||
#define CONFIG_AUTO_COMPLETE |
||||
/* use "hush" command parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_CMD_RUN |
||||
/* PHY */ |
||||
#define CONFIG_EPHY1_PHY_ADDR 4 |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_PHY_MICREL_KSZ9021 |
||||
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" |
||||
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 |
||||
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" |
||||
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run ramboot" |
||||
#endif |
||||
|
||||
/*
|
||||
* arguments passed to the bootm command. The value of |
||||
* CONFIG_BOOTARGS goes into the environment value "bootargs". |
||||
* Do note the value will overide also the chosen node in FDT blob. |
||||
*/ |
||||
#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" |
||||
/* Extra Environment */ |
||||
#define CONFIG_HOSTNAME socfpga_cyclone5 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"verify=n\0" \
|
||||
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"bootimage=uImage\0" \
|
||||
"bootimage=zImage\0" \
|
||||
"fdt_addr=100\0" \
|
||||
"fsloadcmd=ext2load\0" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"fdtimage=socfpga.dtb\0" \
|
||||
"fsloadcmd=ext2load\0" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcroot=/dev/mmcblk0p2\0" \
|
||||
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${mmcroot} rw rootwait;" \
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcload=mmc rescan;" \
|
||||
"load mmc 0:1 ${loadaddr} ${bootimage};" \
|
||||
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
|
||||
"qspiroot=/dev/mtdblock0\0" \
|
||||
"qspirootfstype=jffs2\0" \
|
||||
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" |
||||
|
||||
/* using environment setting for stdin, stdout, stderr */ |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV |
||||
/* Enable the call to overwrite_console() */ |
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
||||
/* Enable overwrite of previous console environment settings */ |
||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
||||
|
||||
/* max number of command args */ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
|
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/*
|
||||
* SDRAM Memory Map |
||||
*/ |
||||
/* We have 1 bank of DRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
/* SDRAM Bank #1 */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
/* SDRAM memory size */ |
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 |
||||
|
||||
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 |
||||
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define UART0_BASE SOCFPGA_UART0_ADDRESS |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550_COM1 UART0_BASE |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define V_NS16550_CLK 1000000 |
||||
#else |
||||
#define V_NS16550_CLK 100000000 |
||||
#endif |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* FLASH |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/*
|
||||
* L4 OSC1 Timer 0 |
||||
*/ |
||||
/* This timer use eosc1 where the clock frequency is fixed
|
||||
* throughout any condition */ |
||||
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
||||
/* reload value when timer count to zero */ |
||||
#define TIMER_LOAD_VAL 0xFFFFFFFF |
||||
/* Timer info */ |
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define CONFIG_SYS_TIMER_RATE 2400000 |
||||
#else |
||||
#define CONFIG_SYS_TIMER_RATE 25000000 |
||||
#endif |
||||
#define CONFIG_SYS_TIMER_COUNTS_DOWN |
||||
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) |
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
|
||||
/*
|
||||
* network support |
||||
*/ |
||||
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET |
||||
#define CONFIG_DESIGNWARE_ETH 1 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_DESIGNWARE_ETH |
||||
#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS |
||||
#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS |
||||
/* console support for network */ |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
/* designware */ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_DW_ALTDESCRIPTOR |
||||
#define CONFIG_DW_SEARCH_PHY |
||||
#define CONFIG_MII |
||||
#define CONFIG_PHY_GIGE |
||||
#define CONFIG_DW_AUTONEG |
||||
#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_PHY_MICREL_KSZ9021 |
||||
/* EMAC controller and PHY used */ |
||||
#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE |
||||
#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR |
||||
#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
||||
#endif /* CONFIG_DESIGNWARE_ETH */ |
||||
|
||||
/*
|
||||
* L4 Watchdog |
||||
*/ |
||||
#define CONFIG_HW_WATCHDOG |
||||
#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 |
||||
#define CONFIG_DESIGNWARE_WATCHDOG |
||||
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
||||
/* Clocks source frequency to watchdog timer */ |
||||
#define CONFIG_DW_WDT_CLOCK_KHZ 25000 |
||||
|
||||
|
||||
/*
|
||||
* SPL "Second Program Loader" aka Initial Software |
||||
*/ |
||||
|
||||
/* Enable building of SPL globally */ |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
|
||||
/* TEXT_BASE for linking the SPL binary */ |
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 |
||||
|
||||
/* Stack size for SPL */ |
||||
#define CONFIG_SPL_STACK_SIZE (4 * 1024) |
||||
|
||||
/* MALLOC size for SPL */ |
||||
#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) |
||||
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_BOARD_INIT |
||||
|
||||
#define CHUNKSZ_CRC32 (1 * 1024) |
||||
|
||||
#define CONFIG_CRC32_VERIFY |
||||
|
||||
/* Linker script for SPL */ |
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" |
||||
|
||||
/* Support for common/libcommon.o in SPL binary */ |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
/* Support for lib/libgeneric.o in SPL binary */ |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
|
||||
/* Support for watchdog */ |
||||
#define CONFIG_SPL_WATCHDOG_SUPPORT |
||||
/* The rest of the configuration is shared */ |
||||
#include <configs/socfpga_common.h> |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ |
||||
|
||||
@ -0,0 +1,259 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Charles Manning <cdhmanning@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf
|
||||
* Note this doc is not entirely accurate. Of particular interest to us is the |
||||
* "header" length field being in U32s and not bytes. |
||||
* |
||||
* "Header" is a structure of the following format. |
||||
* this is positioned at 0x40. |
||||
* |
||||
* Endian is LSB. |
||||
* |
||||
* Offset Length Usage |
||||
* ----------------------- |
||||
* 0x40 4 Validation word 0x31305341 |
||||
* 0x44 1 Version (whatever, zero is fine) |
||||
* 0x45 1 Flags (unused, zero is fine) |
||||
* 0x46 2 Length (in units of u32, including the end checksum). |
||||
* 0x48 2 Zero |
||||
* 0x4A 2 Checksum over the header. NB Not CRC32 |
||||
* |
||||
* At the end of the code we have a 32-bit CRC checksum over whole binary |
||||
* excluding the CRC. |
||||
* |
||||
* Note that the CRC used here is **not** the zlib/Adler crc32. It is the |
||||
* CRC-32 used in bzip2, ethernet and elsewhere. |
||||
* |
||||
* The image is padded out to 64k, because that is what is |
||||
* typically used to write the image to the boot medium. |
||||
*/ |
||||
|
||||
#include "pbl_crc32.h" |
||||
#include "imagetool.h" |
||||
#include <image.h> |
||||
|
||||
#define HEADER_OFFSET 0x40 |
||||
#define VALIDATION_WORD 0x31305341 |
||||
#define PADDED_SIZE 0x10000 |
||||
|
||||
/* To allow for adding CRC, the max input size is a bit smaller. */ |
||||
#define MAX_INPUT_SIZE (PADDED_SIZE - sizeof(uint32_t)) |
||||
|
||||
static uint8_t buffer[PADDED_SIZE]; |
||||
|
||||
static struct socfpga_header { |
||||
uint32_t validation; |
||||
uint8_t version; |
||||
uint8_t flags; |
||||
uint16_t length_u32; |
||||
uint16_t zero; |
||||
uint16_t checksum; |
||||
} header; |
||||
|
||||
/*
|
||||
* The header checksum is just a very simple checksum over |
||||
* the header area. |
||||
* There is still a crc32 over the whole lot. |
||||
*/ |
||||
static uint16_t hdr_checksum(struct socfpga_header *header) |
||||
{ |
||||
int len = sizeof(*header) - sizeof(header->checksum); |
||||
uint8_t *buf = (uint8_t *)header; |
||||
uint16_t ret = 0; |
||||
|
||||
while (--len) |
||||
ret += *buf++; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
|
||||
static void build_header(uint8_t *buf, uint8_t version, uint8_t flags, |
||||
uint16_t length_bytes) |
||||
{ |
||||
header.validation = htole32(VALIDATION_WORD); |
||||
header.version = version; |
||||
header.flags = flags; |
||||
header.length_u32 = htole16(length_bytes/4); |
||||
header.zero = 0; |
||||
header.checksum = htole16(hdr_checksum(&header)); |
||||
|
||||
memcpy(buf, &header, sizeof(header)); |
||||
} |
||||
|
||||
/*
|
||||
* Perform a rudimentary verification of header and return |
||||
* size of image. |
||||
*/ |
||||
static int verify_header(const uint8_t *buf) |
||||
{ |
||||
memcpy(&header, buf, sizeof(header)); |
||||
|
||||
if (le32toh(header.validation) != VALIDATION_WORD) |
||||
return -1; |
||||
if (le16toh(header.checksum) != hdr_checksum(&header)) |
||||
return -1; |
||||
|
||||
return le16toh(header.length_u32) * 4; |
||||
} |
||||
|
||||
/* Sign the buffer and return the signed buffer size */ |
||||
static int sign_buffer(uint8_t *buf, |
||||
uint8_t version, uint8_t flags, |
||||
int len, int pad_64k) |
||||
{ |
||||
uint32_t calc_crc; |
||||
|
||||
/* Align the length up */ |
||||
len = (len + 3) & (~3); |
||||
|
||||
/* Build header, adding 4 bytes to length to hold the CRC32. */ |
||||
build_header(buf + HEADER_OFFSET, version, flags, len + 4); |
||||
|
||||
/* Calculate and apply the CRC */ |
||||
calc_crc = ~pbl_crc32(0, (char *)buf, len); |
||||
|
||||
*((uint32_t *)(buf + len)) = htole32(calc_crc); |
||||
|
||||
if (!pad_64k) |
||||
return len + 4; |
||||
|
||||
return PADDED_SIZE; |
||||
} |
||||
|
||||
/* Verify that the buffer looks sane */ |
||||
static int verify_buffer(const uint8_t *buf) |
||||
{ |
||||
int len; /* Including 32bit CRC */ |
||||
uint32_t calc_crc; |
||||
uint32_t buf_crc; |
||||
|
||||
len = verify_header(buf + HEADER_OFFSET); |
||||
if (len < 0) { |
||||
fprintf(stderr, "Invalid header\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (len < HEADER_OFFSET || len > PADDED_SIZE) { |
||||
fprintf(stderr, "Invalid header length (%i)\n", len); |
||||
return -1; |
||||
} |
||||
|
||||
/*
|
||||
* Adjust length to the base of the CRC. |
||||
* Check the CRC. |
||||
*/ |
||||
len -= 4; |
||||
|
||||
calc_crc = ~pbl_crc32(0, (const char *)buf, len); |
||||
|
||||
buf_crc = le32toh(*((uint32_t *)(buf + len))); |
||||
|
||||
if (buf_crc != calc_crc) { |
||||
fprintf(stderr, "CRC32 does not match (%08x != %08x)\n", |
||||
buf_crc, calc_crc); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* mkimage glue functions */ |
||||
static int socfpgaimage_verify_header(unsigned char *ptr, int image_size, |
||||
struct image_tool_params *params) |
||||
{ |
||||
if (image_size != PADDED_SIZE) |
||||
return -1; |
||||
|
||||
return verify_buffer(ptr); |
||||
} |
||||
|
||||
static void socfpgaimage_print_header(const void *ptr) |
||||
{ |
||||
if (verify_buffer(ptr) == 0) |
||||
printf("Looks like a sane SOCFPGA preloader\n"); |
||||
else |
||||
printf("Not a sane SOCFPGA preloader\n"); |
||||
} |
||||
|
||||
static int socfpgaimage_check_params(struct image_tool_params *params) |
||||
{ |
||||
/* Not sure if we should be accepting fflags */ |
||||
return (params->dflag && (params->fflag || params->lflag)) || |
||||
(params->fflag && (params->dflag || params->lflag)) || |
||||
(params->lflag && (params->dflag || params->fflag)); |
||||
} |
||||
|
||||
static int socfpgaimage_check_image_types(uint8_t type) |
||||
{ |
||||
if (type == IH_TYPE_SOCFPGAIMAGE) |
||||
return EXIT_SUCCESS; |
||||
return EXIT_FAILURE; |
||||
} |
||||
|
||||
/*
|
||||
* To work in with the mkimage framework, we do some ugly stuff... |
||||
* |
||||
* First, socfpgaimage_vrec_header() is called. |
||||
* We prepend a fake header big enough to make the file PADDED_SIZE. |
||||
* This gives us enough space to do what we want later. |
||||
* |
||||
* Next, socfpgaimage_set_header() is called. |
||||
* We fix up the buffer by moving the image to the start of the buffer. |
||||
* We now have some room to do what we need (add CRC and padding). |
||||
*/ |
||||
|
||||
static int data_size; |
||||
#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size) |
||||
|
||||
static int socfpgaimage_vrec_header(struct image_tool_params *params, |
||||
struct image_type_params *tparams) |
||||
{ |
||||
struct stat sbuf; |
||||
|
||||
if (params->datafile && |
||||
stat(params->datafile, &sbuf) == 0 && |
||||
sbuf.st_size <= MAX_INPUT_SIZE) { |
||||
data_size = sbuf.st_size; |
||||
tparams->header_size = FAKE_HEADER_SIZE; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static void socfpgaimage_set_header(void *ptr, struct stat *sbuf, int ifd, |
||||
struct image_tool_params *params) |
||||
{ |
||||
uint8_t *buf = (uint8_t *)ptr; |
||||
|
||||
/*
|
||||
* This function is called after vrec_header() has been called. |
||||
* At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by |
||||
* data_size image bytes. Total = PADDED_SIZE. |
||||
* We need to fix the buffer by moving the image bytes back to |
||||
* the beginning of the buffer, then actually do the signing stuff... |
||||
*/ |
||||
memmove(buf, buf + FAKE_HEADER_SIZE, data_size); |
||||
memset(buf + data_size, 0, FAKE_HEADER_SIZE); |
||||
|
||||
sign_buffer(buf, 0, 0, data_size, 0); |
||||
} |
||||
|
||||
static struct image_type_params socfpgaimage_params = { |
||||
.name = "Altera SOCFPGA preloader support", |
||||
.vrec_header = socfpgaimage_vrec_header, |
||||
.header_size = 0, /* This will be modified by vrec_header() */ |
||||
.hdr = (void *)buffer, |
||||
.check_image_type = socfpgaimage_check_image_types, |
||||
.verify_header = socfpgaimage_verify_header, |
||||
.print_header = socfpgaimage_print_header, |
||||
.set_header = socfpgaimage_set_header, |
||||
.check_params = socfpgaimage_check_params, |
||||
}; |
||||
|
||||
void init_socfpga_image_type(void) |
||||
{ |
||||
register_image_type(&socfpgaimage_params); |
||||
} |
||||
Loading…
Reference in new issue