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@ -47,14 +47,24 @@ |
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#define IPU_SMFC_REG_BASE 0x00050000 |
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#define IPU_DC_REG_BASE 0x00058000 |
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#define IPU_DMFC_REG_BASE 0x00060000 |
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#define IPU_VDI_REG_BASE 0x00680000 |
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#if defined(CONFIG_MX51) || defined(CONFIG_MX53) |
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#define IPU_CPMEM_REG_BASE 0x01000000 |
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#define IPU_LUT_REG_BASE 0x01020000 |
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#define IPU_SRM_REG_BASE 0x01040000 |
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#define IPU_TPM_REG_BASE 0x01060000 |
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#define IPU_DC_TMPL_REG_BASE 0x01080000 |
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#define IPU_ISP_TBPR_REG_BASE 0x010C0000 |
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#define IPU_VDI_REG_BASE 0x00680000 |
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#elif defined(CONFIG_MX6Q) |
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#define IPU_CPMEM_REG_BASE 0x00100000 |
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#define IPU_LUT_REG_BASE 0x00120000 |
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#define IPU_SRM_REG_BASE 0x00140000 |
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#define IPU_TPM_REG_BASE 0x00160000 |
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#define IPU_DC_TMPL_REG_BASE 0x00180000 |
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#define IPU_ISP_TBPR_REG_BASE 0x001C0000 |
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#endif |
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#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET) |
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extern u32 *ipu_dc_tmpl_reg; |
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