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ARM: AM33xx: Move s_init to a common place

Browse Source 
s_init has the same outline for all the AM33xx based
board. So making it generic.
This also helps in addition of new Soc with minimal changes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
master
Heiko Schocher 11 years ago committed by Tom Rini
parent 95cb69faeb
commit 0660481a59
9 changed files with 128 additions and 218 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 62
      arch/arm/cpu/armv7/am33xx/board.c
  2. 6
      arch/arm/cpu/armv7/am33xx/clock_ti814x.c
  3. 6
      arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
  4. 8
      arch/arm/include/asm/arch-am33xx/sys_proto.h
  5. 50
      board/isee/igep0033/board.c
  6. 48
      board/phytec/pcm051/board.c
  7. 80
      board/ti/am335x/board.c
  8. 19
      board/ti/am335x/mux.c
  9. 67
      board/ti/ti814x/evm.c

62
arch/arm/cpu/armv7/am33xx/board.c
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@ -137,7 +137,7 @@ int arch_misc_init(void)
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void rtc32k_enable(void)
static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
@ -153,11 +153,7 @@ void rtc32k_enable(void)
writel((1 << 3) | (1 << 6), &rtc->osc);
}
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
void uart_soft_reset(void)
static void uart_soft_reset(void)
{
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
u32 regval;
@ -174,4 +170,58 @@ void uart_soft_reset(void)
regval |= UART_SMART_IDLE_EN;
writel(regval, &uart_base->uartsyscfg);
}
static void watchdog_disable(void)
{
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
}
#endif
void s_init(void)
{
/*
* The ROM will only have set up sufficient pinmux to allow for the
* first 4KiB NOR to be read, we must finish doing what we know of
* the NOR mux in this space in order to continue.
*/
#ifdef CONFIG_NOR_BOOT
enable_norboot_pin_mux();
#endif
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
watchdog_disable();
timer_init();
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
#endif
#ifdef CONFIG_NOR_BOOT
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
#else
gd = &gdata;
preloader_console_init();
#endif
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
prcm_init();
set_mux_conf_regs();
/* Enable RTC32K clock */
rtc32k_enable();
sdram_init();
#endif
}

6
arch/arm/cpu/armv7/am33xx/clock_ti814x.c
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@ -277,6 +277,12 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
;
/* RTC clocks */
writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
;
}
/*

6
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
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@ -16,8 +16,10 @@
#define CONFIG_SYS_MPUCLK 550
#endif
extern void pll_init(void);
extern void enable_emif_clocks(void);
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
extern void enable_dmm_clocks(void);
#endif /* endif _CLOCKS_AM33XX_H_ */

8
arch/arm/include/asm/arch-am33xx/sys_proto.h
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@ -35,7 +35,11 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size);
void omap_nand_switch_ecc(uint32_t, uint32_t);
void rtc32k_enable(void);
void uart_soft_reset(void);
void set_uart_mux_conf(void);
void set_mux_conf_regs(void);
void sdram_init(void);
u32 wait_on_value(u32, u32, void *, u32);
#ifdef CONFIG_NOR_BOOT
void enable_norboot_pin_mux(void);
#endif
#endif

50
board/isee/igep0033/board.c
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@ -27,8 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
/* MII mode defines */
#define RMII_MODE_ENABLE 0x4D
@ -76,54 +74,22 @@ const struct dpll_params *get_dpll_ddr_params(void)
return &dpll_ddr;
}
#endif
/*
* Early system init of muxing and clocks.
*/
void s_init(void)
void set_uart_mux_conf(void)
{
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
setup_clocks_for_console();
enable_uart0_pin_mux();
}
uart_soft_reset();
gd = &gdata;
preloader_console_init();
prcm_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* Configure board pin mux */
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
void sdram_init(void)
{
config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
#endif
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.

48
board/phytec/pcm051/board.c
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@ -30,8 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0xA
@ -85,57 +83,27 @@ static struct emif_regs ddr3_emif_reg_data = {
.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
#endif
/*
* early system init of muxing and clocks.
*/
void s_init(void)
void set_uart_mux_conf(void)
{
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
/*
* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
enable_uart0_pin_mux();
uart_soft_reset();
gd = &gdata;
preloader_console_init();
}
void set_mux_conf_regs(void)
{
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
enable_board_pin_mux();
}
void sdram_init(void)
{
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
#endif
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.

80
board/ti/am335x/board.c
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@ -30,8 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0x3A
@ -269,56 +267,8 @@ const struct dpll_params *get_dpll_ddr_params(void)
return &dpll_ddr;
}
#endif
/*
* early system init of muxing and clocks.
*/
void s_init(void)
void set_uart_mux_conf(void)
{
__maybe_unused struct am335x_baseboard_id header;
/*
* The ROM will only have set up sufficient pinmux to allow for the
* first 4KiB NOR to be read, we must finish doing what we know of
* the NOR mux in this space in order to continue.
*/
#ifdef CONFIG_NOR_BOOT
asm("stmfd sp!, {r2 - r4}");
asm("movw r4, #0x8A4");
asm("movw r3, #0x44E1");
asm("orr r4, r4, r3, lsl #16");
asm("mov r2, #9");
asm("mov r3, #8");
asm("gpmc_mux: str r2, [r4], #4");
asm("subs r3, r3, #1");
asm("bne gpmc_mux");
asm("ldmfd sp!, {r2 - r4}");
#endif
#ifdef CONFIG_SPL_BUILD
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
save_omap_boot_params();
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
/* Setup the PLLs and the clocks for the peripherals */
setup_clocks_for_console();
#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
@ -337,29 +287,25 @@ void s_init(void)
#ifdef CONFIG_SERIAL6
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
}
uart_soft_reset();
void set_mux_conf_regs(void)
{
__maybe_unused struct am335x_baseboard_id header;
#if defined(CONFIG_NOR_BOOT)
/* We want our console now. */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
#else
gd = &gdata;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
preloader_console_init();
#endif
enable_board_pin_mux(&header);
}
prcm_init();
void sdram_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
/* Enable RTC32K clock */
rtc32k_enable();
enable_board_pin_mux(&header);
if (board_is_evm_sk(&header)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
@ -383,8 +329,8 @@ void s_init(void)
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
#endif
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.

19
board/ti/am335x/mux.c
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@ -239,6 +239,25 @@ static struct module_pin_mux bone_norcape_pin_mux[] = {
};
#endif
#if defined(CONFIG_NOR_BOOT)
static struct module_pin_mux norboot_pin_mux[] = {
{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
{-1},
};
void enable_norboot_pin_mux(void)
{
configure_module_pin_mux(norboot_pin_mux);
}
#endif
void enable_uart0_pin_mux(void)
{

67
board/ti/ti814x/evm.c
Unescape View File

@ -27,30 +27,10 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
#endif
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
static void uart_enable(void)
{
/* UART softreset */
uart_soft_reset();
}
static void wdt_disable(void)
{
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
}
static const struct cmd_control evm_ddr2_cctrl_data = {
.cmd0csratio = 0x80,
.cmd0dldiff = 0x04,
@ -100,63 +80,32 @@ static const struct ddr_data evm_ddr2_data = {
.datauserank0delay = 1,
.datadldiff0 = 0x4,
};
#endif
/*
* early system init of muxing and clocks.
*/
void s_init(void)
void set_uart_mux_conf(void)
{
#ifdef CONFIG_SPL_BUILD
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
wdt_disable();
/* Enable timer */
timer_init();
setup_clocks_for_console();
/* Set UART pins */
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
/* Set MMC pins */
enable_mmc1_pin_mux();
/* Set Ethernet pins */
enable_enet_pin_mux();
}
/* Enable UART */
uart_enable();
gd = &gdata;
preloader_console_init();
/* Setup the PLLs and the clocks for the peripherals */
prcm_init();
/* Enable RTC32K clock */
rtc32k_enable();
void sdram_init(void)
{
config_dmm(&evm_lisa_map_regs);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif0_regs, 0);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif1_regs, 1);
#endif
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.

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