Add Sysam Amcore m68k-based board support. Signed-off-by: Angelo Dureghello <angelo@sysam.it>master
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if TARGET_AMCORE |
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config SYS_CPU |
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string |
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default "mcf530x" |
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config SYS_BOARD |
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string |
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default "amcore" |
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config SYS_VENDOR |
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string |
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default "sysam" |
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config SYS_CONFIG_NAME |
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string |
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default "amcore" |
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endif |
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AMCORE BOARD |
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M: Angelo Dureghello <angelo@sysam.it> |
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S: Maintained |
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F: board/sysam/amcore/ |
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F: include/configs/amcore.h |
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F: configs/amcore_defconfig |
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#
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# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = amcore.o
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/*
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* Board functions for Sysam AMCORE (MCF5307 based) board |
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* |
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* (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* This file copies memory testdram() from sandburst/common/sb_common.c |
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*/ |
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#include <common.h> |
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#include <asm/immap.h> |
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#include <asm/io.h> |
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void init_lcd(void) |
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{ |
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/* setup for possible K0108 lcd connected on the parallel port */ |
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sim_t *sim = (sim_t *)(MMAP_SIM); |
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out_be16(&sim->par, 0x300); |
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gpio_t *gpio = (gpio_t *)(MMAP_GPIO); |
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out_be16(&gpio->paddr, 0xfcff); |
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out_be16(&gpio->padat, 0x0c00); |
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} |
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int checkboard(void) |
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{ |
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puts("Board: "); |
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puts("AMCORE v.001(alpha)\n"); |
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init_lcd(); |
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return 0; |
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} |
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/*
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* in initdram we are here executing from flash |
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* case 1: |
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* is with no ACR/flash cache enabled |
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* nop = 40ns (scope measured) |
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*/ |
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void fudelay(int usec) |
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{ |
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while (usec--) |
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asm volatile ("nop"); |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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u32 dramsize, RC; |
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sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC); |
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/*
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* SDRAM MT48LC4M32B2 details |
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* Memory block 0: 16 MB of SDRAM at address $00000000 |
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* Port size: 32-bit port |
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* |
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* Memory block 0 wired as follows: |
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* CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 |
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* SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 |
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* |
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* Ensure that there is a delay of at least 100 microseconds from |
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* processor reset to the following code so that the SDRAM is ready |
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* for commands. |
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*/ |
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fudelay(100); |
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/*
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* DCR |
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* set proper RC as per specification |
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*/ |
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RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; |
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RC = (RC * 15) >> 4; |
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/* 0x8000 is the faster option */ |
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out_be16(&dc->dcr, 0x8200 | RC); |
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/*
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* DACR0, page mode continuous, CMD on A20 0x0300 |
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*/ |
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out_be32(&dc->dacr0, 0x00003304); |
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dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; |
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out_be32(&dc->dmr0, dramsize|1); |
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/* issue a PRECHARGE ALL */ |
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out_be32(&dc->dacr0, 0x0000330c); |
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out_be32((u32 *)0x00000004, 0xbeaddeed); |
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/* issue AUTOREFRESH */ |
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out_be32(&dc->dacr0, 0x0000b304); |
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/* let refresh occour */ |
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fudelay(1); |
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out_be32(&dc->dacr0, 0x0000b344); |
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out_be32((u32 *)0x00000c00, 0xbeaddeed); |
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return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); |
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} |
@ -0,0 +1,7 @@ |
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#
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# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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CONFIG_SYS_TEXT_BASE = 0xffc00000
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@ -0,0 +1,87 @@ |
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/* |
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* Linker script for Sysam AMCORE board |
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* |
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* (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_ARCH(m68k) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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.text : |
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{ |
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arch/m68k/cpu/mcf530x/start.o (.text) |
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. = DEFINED(env_offset) ? env_offset : .; |
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common/env_embedded.o (.text) |
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*(.text) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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__got_start = .; |
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KEEP(*(.got)) |
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__got_end = .; |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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.data : |
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{ |
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*(.data) |
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*(.sdata) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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_sbss = .; |
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*(.sbss*) |
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*(.bss*) |
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*(COMMON) |
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. = ALIGN(4); |
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_ebss = .; |
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} |
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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CONFIG_M68K=y |
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CONFIG_TARGET_AMCORE=y |
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/*
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* Sysam AMCORE board configuration |
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* |
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* (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __AMCORE_CONFIG_H |
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#define __AMCORE_CONFIG_H |
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#define CONFIG_AMCORE |
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#define CONFIG_HOSTNAME AMCORE |
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#define CONFIG_SYS_GENERIC_BOARD |
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#define CONFIG_MCF530x |
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#define CONFIG_M5307 |
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#define CONFIG_MCFTMR |
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#define CONFIG_MCFUART |
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#define CONFIG_SYS_UART_PORT 0 |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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#define CONFIG_BOOTDELAY 1 |
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#define CONFIG_BOOTCOMMAND "bootm ffc20000" |
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#include <config_cmd_default.h> |
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#undef CONFIG_CMD_AES |
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#undef CONFIG_CMD_BOOTD |
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#undef CONFIG_CMD_NET |
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#undef CONFIG_CMD_NFS |
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#undef CONFIG_CMD_FPGA |
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#undef CONFIG_CMD_XIMG |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_TIMER |
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#define CONFIG_CMD_DIAG |
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#define CONFIG_SYS_PROMPT "amcore $ " |
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/* undef to save memory */ |
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#undef CONFIG_SYS_LONGHELP |
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#if defined(CONFIG_CMD_KGDB) |
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/* Console I/O buff. size */ |
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#define CONFIG_SYS_CBSIZE 1024 |
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#else |
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#define CONFIG_SYS_CBSIZE 256 |
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#endif |
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/* Print buffer size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
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sizeof(CONFIG_SYS_PROMPT)+16) |
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/* max number of command args */ |
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#define CONFIG_SYS_MAXARGS 16 |
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/* Boot argument buffer size */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */ |
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
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#define CONFIG_LOOPW 1 /* enable loopw command */ |
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
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#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ |
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#define CONFIG_SYS_MEMTEST_START 0x0 |
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#define CONFIG_SYS_MEMTEST_END 0x1000000 |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_SYS_CLK 45000000 |
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#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) |
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/* Register Base Addrs */ |
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#define CONFIG_SYS_MBAR 0x10000000 |
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/* Definitions for initial stack pointer and data area (in DPRAM) */ |
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
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/* size of internal SRAM */ |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
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GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_SDRAM_SIZE 0x1000000 |
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#define CONFIG_SYS_FLASH_BASE 0xffc00000 |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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/* amcore design has flash data bytes wired swapped */ |
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#define CONFIG_SYS_WRITE_SWAPPED_DATA |
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/* reserve 128-4KB */ |
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
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#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) |
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) |
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#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ |
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CONFIG_SYS_MONITOR_LEN) |
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#define CONFIG_ENV_SIZE 0x1000 |
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#define CONFIG_ENV_SECT_SIZE 0x1000 |
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/* memory map space for linux boot data */ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
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/*
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* Cache Configuration |
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* |
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* Special 8K version 3 core cache. |
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* This is a single unified instruction/data cache. |
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* sdram - single region - no masks |
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*/ |
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#define CONFIG_SYS_CACHELINE_SIZE 16 |
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
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CONFIG_SYS_INIT_RAM_SIZE - 8) |
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
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CONFIG_SYS_INIT_RAM_SIZE - 4) |
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
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#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ |
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CF_ACR_EN) |
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ |
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CF_CACR_EC) |
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/* CS0 - AMD Flash, address 0xffc00000 */ |
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#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) |
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/* 4MB, AA=0,V=1 C/I BIT for errata */ |
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#define CONFIG_SYS_CS0_MASK 0x003f0001 |
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/* WS=10, AA=1, PS=16bit (10) */ |
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#define CONFIG_SYS_CS0_CTRL 0x1980 |
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/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ |
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#define CONFIG_SYS_CS1_BASE 0x3000 |
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#define CONFIG_SYS_CS1_MASK 0x00070001 |
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#define CONFIG_SYS_CS1_CTRL 0x0100 |
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#endif /* __AMCORE_CONFIG_H */ |
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