@ -37,7 +37,7 @@
DECLARE_GLOBAL_DATA_PTR ;
u32 * const omap4_revision = ( u32 * ) OMAP4_SRAM_SCRATCH_OMAP4_REV ;
u32 * const omap_si_rev = ( u32 * ) OMAP4_SRAM_SCRATCH_OMAP4_REV ;
static const struct gpio_bank gpio_bank_44xx [ 6 ] = {
{ ( void * ) OMAP44XX_GPIO1_BASE , METHOD_GPIO_24XX } ,
@ -129,40 +129,40 @@ void init_omap_revision(void)
switch ( arm_rev ) {
case MIDR_CORTEX_A9_R0P1 :
* omap4_revision = OMAP4430_ES1_0 ;
* omap_si_rev = OMAP4430_ES1_0 ;
break ;
case MIDR_CORTEX_A9_R1P2 :
switch ( readl ( CONTROL_ID_CODE ) ) {
case OMAP4_CONTROL_ID_CODE_ES2_0 :
* omap4_revision = OMAP4430_ES2_0 ;
* omap_si_rev = OMAP4430_ES2_0 ;
break ;
case OMAP4_CONTROL_ID_CODE_ES2_1 :
* omap4_revision = OMAP4430_ES2_1 ;
* omap_si_rev = OMAP4430_ES2_1 ;
break ;
case OMAP4_CONTROL_ID_CODE_ES2_2 :
* omap4_revision = OMAP4430_ES2_2 ;
* omap_si_rev = OMAP4430_ES2_2 ;
break ;
default :
* omap4_revision = OMAP4430_ES2_0 ;
* omap_si_rev = OMAP4430_ES2_0 ;
break ;
}
break ;
case MIDR_CORTEX_A9_R1P3 :
* omap4_revision = OMAP4430_ES2_3 ;
* omap_si_rev = OMAP4430_ES2_3 ;
break ;
case MIDR_CORTEX_A9_R2P10 :
switch ( readl ( CONTROL_ID_CODE ) ) {
case OMAP4460_CONTROL_ID_CODE_ES1_1 :
* omap4_revision = OMAP4460_ES1_1 ;
* omap_si_rev = OMAP4460_ES1_1 ;
break ;
case OMAP4460_CONTROL_ID_CODE_ES1_0 :
default :
* omap4_revision = OMAP4460_ES1_0 ;
* omap_si_rev = OMAP4460_ES1_0 ;
break ;
}
break ;
default :
* omap4_revision = OMAP4430_SILICON_ID_INVALID ;
* omap_si_rev = OMAP4430_SILICON_ID_INVALID ;
break ;
}
}