Tom Rini
11 years ago
commit
0a64bc20f7
@ -1,46 +0,0 @@ |
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/*
|
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
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* Scott McNutt <smcnutt@psyent.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#include <nios2-io.h> |
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#include <status_led.h> |
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/* The LED port is configured as output only, so we
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* must track the state manually. |
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*/ |
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static led_id_t val = 0; |
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|
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void __led_init (led_id_t mask, int state) |
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{ |
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nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; |
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if (state == STATUS_LED_ON) |
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val &= ~mask; |
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else |
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val |= mask; |
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writel (val, &pio->data); |
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} |
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|
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void __led_set (led_id_t mask, int state) |
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{ |
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nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; |
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if (state == STATUS_LED_ON) |
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val &= ~mask; |
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else |
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val |= mask; |
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writel (val, &pio->data); |
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} |
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|
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void __led_toggle (led_id_t mask) |
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{ |
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nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; |
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val ^= mask; |
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writel (val, &pio->data); |
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} |
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@ -1,78 +1,89 @@ |
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/*
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* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> |
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* This header is generated by sopc2dts |
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* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl> |
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* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This file is generated by sopc-create-config-files. |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CUSTOM_FPGA_H_ |
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#define _CUSTOM_FPGA_H_ |
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|
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/* generated from std_1c20.sopc */ |
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/* cpu.data_master is a altera_nios2 */ |
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#define CONFIG_SYS_CLK_FREQ 50000000 |
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#define CONFIG_SYS_RESET_ADDR 0x00000000 |
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#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 |
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#define CONFIG_SYS_ICACHE_SIZE 4096 |
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#define CONFIG_SYS_ICACHELINE_SIZE 32 |
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#define CONFIG_SYS_DCACHE_SIZE 2048 |
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#define CONFIG_SYS_DCACHELINE_SIZE 4 |
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|
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/* sdram.s1 is a altera_avalon_new_sdram_controller */ |
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#define CONFIG_SYS_SDRAM_BASE 0x01000000 |
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#define CONFIG_SYS_SDRAM_SIZE 0x01000000 |
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|
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/* uart1.s1 is a altera_avalon_uart */ |
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#define CONFIG_SYS_UART_BASE 0x82120840 |
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#define CONFIG_SYS_UART_FREQ 50000000 |
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#define CONFIG_SYS_UART_BAUD 115200 |
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|
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/* lan91c111.s1 is a altera_avalon_lan91c111 */ |
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#define CONFIG_SMC91111_BASE 0x82110300 |
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#define CONFIG_SMC91111 |
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#define CONFIG_SMC_USE_32_BIT |
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|
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/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ |
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#define EPCS_CONTROLLER_REG_BASE 0x82100200 |
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#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } |
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#define CONFIG_ALTERA_SPI |
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#define CONFIG_CMD_SPI |
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#define CONFIG_CMD_SF |
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#define CONFIG_SF_DEFAULT_SPEED 30000000 |
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#define CONFIG_SPI_FLASH |
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#define CONFIG_SPI_FLASH_STMICRO |
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/* generated from qsys_ghrd_3c120.sopcinfo */ |
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/* Dumping slaves of cpu.data_master */ |
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/* cpu.jtag_debug_module is a altera_nios2_qsys */ |
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#define CONFIG_SYS_CLK_FREQ 125000000 |
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#define CONFIG_SYS_DCACHE_SIZE 32768 |
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#define CONFIG_SYS_DCACHELINE_SIZE 32 |
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#define CONFIG_SYS_ICACHELINE_SIZE 32 |
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#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020 |
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#define CONFIG_SYS_ICACHE_SIZE 32768 |
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#define CONFIG_SYS_RESET_ADDR 0xc2800000 |
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#define IO_REGION_BASE 0xE0000000 |
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|
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/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */ |
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/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */ |
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/* ddr2_bot.s1 is a altmemddr2 */ |
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#define CONFIG_SYS_SDRAM_BASE 0xD0000000 |
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000 |
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/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */ |
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/* Dumping slaves of pb_cpu_to_io.m0 */ |
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/* timer_1ms.s1 is a altera_avalon_timer */ |
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#define CONFIG_SYS_TIMER_IRQ 11 |
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#define CONFIG_SYS_TIMER_FREQ 125000000 |
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#define CONFIG_SYS_TIMER_BASE 0xE8400000 |
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|
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/* sysid.control_slave is a altera_avalon_sysid_qsys */ |
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#define CONFIG_SYS_SYSID_BASE 0xE8004D40 |
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/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ |
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#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 |
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#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50 |
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|
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/* tse_mac.control_port is a triple_speed_ethernet */ |
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#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048 |
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#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800 |
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#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400 |
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#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048 |
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#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000 |
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#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000 |
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#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000 |
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#define CONFIG_ALTERA_TSE |
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#define CONFIG_MII |
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#define CONFIG_CMD_MII |
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#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18 |
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#define CONFIG_SYS_ALTERA_TSE_FLAGS 1 |
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/* uart.s1 is a altera_avalon_uart */ |
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#define CONFIG_SYS_UART_BAUD 115200 |
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#define CONFIG_SYS_UART_BASE 0xE8004C80 |
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#define CONFIG_SYS_UART_FREQ 62500000 |
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/* user_led_pio_8out.s1 is a altera_avalon_pio */ |
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#define USER_LED_PIO_8OUT_BASE 0xE8004CC0 |
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/* led_pio.s1 is a altera_avalon_pio */ |
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#define LED_PIO_BASE 0x82120870 |
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#define LED_PIO_WIDTH 8 |
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#define LED_PIO_RSTVAL 0x0 |
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/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */ |
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#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0 |
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#define USER_DIPSW_PIO_8IN_IRQ 8 |
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|
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/* high_res_timer.s1 is a altera_avalon_timer */ |
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#define CONFIG_SYS_TIMER_BASE 0x82120820 |
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#define CONFIG_SYS_TIMER_IRQ 3 |
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#define CONFIG_SYS_TIMER_FREQ 50000000 |
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/* user_pb_pio_4in.s1 is a altera_avalon_pio */ |
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#define USER_PB_PIO_4IN_BASE 0xE8004D00 |
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#define USER_PB_PIO_4IN_IRQ 9 |
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/* cfi_flash_64m.uas is a altera_generic_tristate_controller */ |
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#define CFI_FLASH_64M_BASE 0xE0000000 |
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|
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/* ext_flash.s1 is a altera_avalon_cfi_flash */ |
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#define CONFIG_SYS_FLASH_BASE 0x80000000 |
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#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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#define CONFIG_SYS_FLASH_PROTECTION |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 |
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/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */ |
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#define CONFIG_SYS_SRAM_BASE 0x02000000 |
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#define CONFIG_SYS_SRAM_SIZE 0x00100000 |
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/* sysid.control_slave is a altera_avalon_sysid */ |
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#define CONFIG_SYS_SYSID_BASE 0x821208b8 |
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#define CONFIG_SYS_MAX_FLASH_SECT 512 |
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#endif /* _CUSTOM_FPGA_H_ */ |
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@ -1,21 +0,0 @@ |
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/* |
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* text_base |
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* |
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* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
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* |
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <config.h> |
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#ifdef CONFIG_SYS_MONITOR_BASE |
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.text |
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/* text base used in link script u-boot.lds */ |
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.global text_base
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.equ text_base,CONFIG_SYS_MONITOR_BASE |
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/* dummy func to let linker include this file */ |
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.global text_base_hook
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text_base_hook: |
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ret |
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#endif |
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@ -1,118 +0,0 @@ |
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/* |
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
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* Scott McNutt <smcnutt@psyent.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_FORMAT("elf32-littlenios2") |
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OUTPUT_ARCH(nios2) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = text_base; |
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.text : |
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{ |
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arch/nios2/cpu/start.o (.text) |
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*(.text) |
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*(.text.*) |
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*(.gnu.linkonce.t*) |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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*(.gnu.linkonce.r*) |
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} |
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. = ALIGN (4); |
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_etext = .; |
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PROVIDE (etext = .); |
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/* CMD TABLE - sandwich this in between text and data so |
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* the initialization code relocates the command table as |
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* well -- admittedly, this is just pure laziness ;-) |
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*/ |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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|
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/* INIT DATA sections - "Small" data (see the gcc -G option) |
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* is always gp-relative. Here we make all init data sections |
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* adjacent to simplify the startup code -- and provide |
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* the global pointer for gp-relative access. |
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*/ |
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_data = .; |
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.data : |
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{ |
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*(.data) |
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*(.data.*) |
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*(.gnu.linkonce.d*) |
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} |
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. = ALIGN(16); |
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_gp = .; /* Global pointer addr */ |
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PROVIDE (gp = .); |
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.sdata : |
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{ |
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*(.sdata) |
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*(.sdata.*) |
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*(.gnu.linkonce.s.*) |
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} |
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. = ALIGN(4); |
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|
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_edata = .; |
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PROVIDE (edata = .); |
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|
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/* UNINIT DATA - Small uninitialized data is first so it's |
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* adjacent to sdata and can be referenced via gp. The normal |
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* bss follows. We keep it adjacent to simplify init code. |
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*/ |
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__bss_start = .; |
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.sbss (NOLOAD) : |
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{ |
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*(.sbss) |
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*(.sbss.*) |
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*(.gnu.linkonce.sb.*) |
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*(.scommon) |
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} |
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. = ALIGN(4); |
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.bss (NOLOAD) : |
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{ |
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*(.bss) |
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*(.bss.*) |
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*(.dynbss) |
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*(COMMON) |
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*(.scommon) |
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} |
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. = ALIGN(4); |
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__bss_end = .; |
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PROVIDE (end = .); |
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|
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/* DEBUG -- symbol table, string table, etc. etc. |
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*/ |
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.stab 0 : { *(.stab) } |
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.stabstr 0 : { *(.stabstr) } |
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.stab.excl 0 : { *(.stab.excl) } |
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.stab.exclstr 0 : { *(.stab.exclstr) } |
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.stab.index 0 : { *(.stab.index) } |
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.stab.indexstr 0 : { *(.stab.indexstr) } |
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.comment 0 : { *(.comment) } |
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.debug 0 : { *(.debug) } |
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.line 0 : { *(.line) } |
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.debug_srcinfo 0 : { *(.debug_srcinfo) } |
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.debug_sfnames 0 : { *(.debug_sfnames) } |
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.debug_aranges 0 : { *(.debug_aranges) } |
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.debug_pubnames 0 : { *(.debug_pubnames) } |
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.debug_info 0 : { *(.debug_info) } |
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.debug_abbrev 0 : { *(.debug_abbrev) } |
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.debug_line 0 : { *(.debug_line) } |
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.debug_frame 0 : { *(.debug_frame) } |
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.debug_str 0 : { *(.debug_str) } |
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.debug_loc 0 : { *(.debug_loc) } |
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.debug_macinfo 0 : { *(.debug_macinfo) } |
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.debug_weaknames 0 : { *(.debug_weaknames) } |
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.debug_funcnames 0 : { *(.debug_funcnames) } |
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.debug_typenames 0 : { *(.debug_typenames) } |
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.debug_varnames 0 : { *(.debug_varnames) } |
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} |
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@ -1,153 +0,0 @@ |
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/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
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* Scott McNutt <smcnutt@psyent.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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/*************************************************************************
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* Altera Nios2 Standard Peripherals |
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************************************************************************/ |
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#ifndef __NIOS2IO_H__ |
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#define __NIOS2IO_H__ |
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|
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/*------------------------------------------------------------------------
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* UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
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*----------------------------------------------------------------------*/ |
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typedef volatile struct nios_uart_t { |
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unsigned rxdata; /* Rx data reg */ |
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unsigned txdata; /* Tx data reg */ |
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unsigned status; /* Status reg */ |
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unsigned control; /* Control reg */ |
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unsigned divisor; /* Baud rate divisor reg */ |
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unsigned endofpacket; /* End-of-packet reg */ |
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}nios_uart_t; |
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|
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/* status register */ |
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#define NIOS_UART_PE (1 << 0) /* parity error */ |
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#define NIOS_UART_FE (1 << 1) /* frame error */ |
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#define NIOS_UART_BRK (1 << 2) /* break detect */ |
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#define NIOS_UART_ROE (1 << 3) /* rx overrun */ |
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#define NIOS_UART_TOE (1 << 4) /* tx overrun */ |
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#define NIOS_UART_TMT (1 << 5) /* tx empty */ |
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#define NIOS_UART_TRDY (1 << 6) /* tx ready */ |
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#define NIOS_UART_RRDY (1 << 7) /* rx ready */ |
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#define NIOS_UART_E (1 << 8) /* exception */ |
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#define NIOS_UART_DCTS (1 << 10) /* cts change */ |
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#define NIOS_UART_CTS (1 << 11) /* cts */ |
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#define NIOS_UART_EOP (1 << 12) /* eop detected */ |
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|
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/* control register */ |
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#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ |
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#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ |
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#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ |
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#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ |
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#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ |
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#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ |
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#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ |
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#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ |
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#define NIOS_UART_IE (1 << 8) /* exception int ena */ |
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#define NIOS_UART_TBRK (1 << 9) /* transmit break */ |
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#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ |
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#define NIOS_UART_RTS (1 << 11) /* rts */ |
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#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ |
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|
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|
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/*------------------------------------------------------------------------
|
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* TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
|
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*----------------------------------------------------------------------*/ |
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typedef volatile struct nios_timer_t { |
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unsigned status; /* Timer status reg */ |
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unsigned control; /* Timer control reg */ |
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unsigned periodl; /* Timeout period low */ |
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unsigned periodh; /* Timeout period high */ |
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unsigned snapl; /* Snapshot low */ |
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unsigned snaph; /* Snapshot high */ |
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}nios_timer_t; |
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|
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/* status register */ |
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#define NIOS_TIMER_TO (1 << 0) /* Timeout */ |
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#define NIOS_TIMER_RUN (1 << 1) /* Timer running */ |
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|
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/* control register */ |
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#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */ |
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#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */ |
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#define NIOS_TIMER_START (1 << 2) /* Start timer */ |
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#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ |
||||
|
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|
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/*------------------------------------------------------------------------
|
||||
* PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
|
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*----------------------------------------------------------------------*/ |
||||
typedef volatile struct nios_pio_t { |
||||
unsigned int data; /* Data value at each PIO in/out */ |
||||
unsigned int direction; /* Data direct. for each PIO bit */ |
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unsigned int interruptmask; /* Per-bit IRQ enable/disable */ |
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unsigned int edgecapture; /* Per-bit sync. edge detect & hold */ |
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}nios_pio_t; |
||||
|
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/* direction register */ |
||||
#define NIOS_PIO_OUT (1) /* PIO bit is output */ |
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#define NIOS_PIO_IN (0) /* PIO bit is input */ |
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|
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|
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/*------------------------------------------------------------------------
|
||||
* SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
|
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*----------------------------------------------------------------------*/ |
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typedef volatile struct nios_spi_t { |
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unsigned rxdata; /* Rx data reg */ |
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unsigned txdata; /* Tx data reg */ |
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unsigned status; /* Status reg */ |
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unsigned control; /* Control reg */ |
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unsigned reserved; /* (master only) */ |
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unsigned slaveselect; /* SPI slave select mask (master only) */ |
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}nios_spi_t; |
||||
|
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/* status register */ |
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#define NIOS_SPI_ROE (1 << 3) /* rx overrun */ |
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#define NIOS_SPI_TOE (1 << 4) /* tx overrun */ |
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#define NIOS_SPI_TMT (1 << 5) /* tx empty */ |
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#define NIOS_SPI_TRDY (1 << 6) /* tx ready */ |
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#define NIOS_SPI_RRDY (1 << 7) /* rx ready */ |
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#define NIOS_SPI_E (1 << 8) /* exception */ |
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|
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/* control register */ |
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#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */ |
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#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */ |
||||
#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */ |
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#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */ |
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#define NIOS_SPI_IE (1 << 8) /* exception int ena */ |
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#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ |
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* JTAG UART |
||||
*----------------------------------------------------------------------*/ |
||||
typedef volatile struct nios_jtag_t { |
||||
unsigned data; /* Data register */ |
||||
unsigned control; /* Control register */ |
||||
}nios_jtag_t; |
||||
|
||||
/* data register */ |
||||
#define NIOS_JTAG_RVALID (1<<15) /* Read valid */ |
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#define NIOS_JTAG_DATA(d) ((d)&0x0ff) /* Read data */ |
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#define NIOS_JTAG_RAVAIL(d) ((d)>>16) /* Read space avail */ |
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|
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/* control register */ |
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#define NIOS_JTAG_RE (1 << 0) /* read intr enable */ |
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#define NIOS_JTAG_WE (1 << 1) /* write intr enable */ |
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#define NIOS_JTAG_RI (1 << 8) /* read intr pending */ |
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#define NIOS_JTAG_WI (1 << 9) /* write intr pending*/ |
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#define NIOS_JTAG_AC (1 << 10) /* activity indicator */ |
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#define NIOS_JTAG_RRDY (1 << 12) /* read available */ |
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#define NIOS_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */ |
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|
||||
/*------------------------------------------------------------------------
|
||||
* SYSTEM ID |
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*----------------------------------------------------------------------*/ |
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typedef volatile struct nios_sysid_t { |
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unsigned id; /* The system build id*/ |
||||
unsigned timestamp; /* Timestamp */ |
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}nios_sysid_t; |
||||
|
||||
#endif /* __NIOS2IO_H__ */ |
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@ -1,99 +0,0 @@ |
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/*
|
||||
* (C) Copyright 2006, Imagos S.a.s <www.imagos.it> |
||||
* Renato Andreola <renato.andreola@imagos.it> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*************************************************************************
|
||||
* Altera NiosII YANU serial interface by Imagos |
||||
* please see http://www.opencores.org/project,yanu for
|
||||
* information/downloads |
||||
************************************************************************/ |
||||
|
||||
#ifndef __NIOS2_YANU_H__ |
||||
#define __NIOS2_YANU_H__ |
||||
|
||||
#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ |
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#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ |
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#define YANU_FIFO_SIZE (16) |
||||
#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) |
||||
#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) |
||||
|
||||
#define YANU_RXFIFO_DLY (10*11) |
||||
#define YANU_TXFIFO_THR (10) |
||||
#define YANU_DATA_CHAR_MASK (0xFF) |
||||
|
||||
/* data register */ |
||||
#define YANU_DATA_OFFSET (0) /* data register offset */ |
||||
|
||||
#define YANU_CONTROL_OFFSET (4) /* control register offset */ |
||||
/* interrupt enable */ |
||||
#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ |
||||
#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ |
||||
#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ |
||||
#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ |
||||
#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ |
||||
#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ |
||||
/* control bits */ |
||||
#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ |
||||
#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) /* number of rx/tx bits per word. 3 bit unsigned integer */ |
||||
#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */ |
||||
#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit transmission/reception */ |
||||
#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */ |
||||
#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */ |
||||
#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */ |
||||
#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */ |
||||
/* tuning part */ |
||||
#define YANU_CONTROL_RDYDLY (1<<14) /* delay from "first" before setting rrdy (in bit) */ |
||||
#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */ |
||||
#define YANU_CONTROL_TXTHR (1<<22) /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */ |
||||
#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */ |
||||
|
||||
#define YANU_BAUD_OFFSET (8) /* baud register offset */ |
||||
#define YANU_BAUDM (1<<0) /* baud mantissa lsb */ |
||||
#define YANU_BAUDM_N (12) /* ...its bit filed length */ |
||||
#define YANU_BAUDE (1<<12) /* baud exponent lsb */ |
||||
#define YANU_BAUDE_N (4) /* ...its bit field length */ |
||||
|
||||
#define YANU_ACTION_OFFSET (12) /* action register... write only */ |
||||
#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */ |
||||
#define YANU_ACTION_ROE (1<<1) /* reset oe */ |
||||
#define YANU_ACTION_RBRK (1<<2) /* reset brk */ |
||||
#define YANU_ACTION_RFE (1<<3) /* reset fe */ |
||||
#define YANU_ACTION_RPE (1<<4) /* reset pe */ |
||||
#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */ |
||||
#define YANU_ACTION_SOE (1<<6) /* set oe */ |
||||
#define YANU_ACTION_SBRK (1<<7) /* set brk */ |
||||
#define YANU_ACTION_SFE (1<<8) /* set fe */ |
||||
#define YANU_ACTION_SPE (1<<9) /* set pe */ |
||||
#define YANU_ACTION_RFIFO_PULL (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */ |
||||
#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */ |
||||
#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */ |
||||
#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */ |
||||
#define YANU_ACTION_STRDY (1<<14) /* set trdy */ |
||||
|
||||
#define YANU_STATUS_OFFSET (16) |
||||
#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */ |
||||
#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */ |
||||
#define YANU_STATUS_OE (1<<2) /* rx overrun error */ |
||||
#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */ |
||||
#define YANU_STATUS_FE (1<<4) /* rx framing error flag */ |
||||
#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */ |
||||
#define YANU_RFIFO_CHARS_POS (6) |
||||
#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) /* number of chars into rx fifo */ |
||||
#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ |
||||
#define YANU_TFIFO_CHARS_POS (11) |
||||
#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) /* number of chars into tx fifo */ |
||||
#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ |
||||
|
||||
typedef volatile struct yanu_uart_t { |
||||
volatile unsigned data; |
||||
volatile unsigned control; /* control register (RW) 32-bit */ |
||||
volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */ |
||||
volatile unsigned action; /* action register (W) 32-bit */ |
||||
volatile unsigned status; /* status register (R) 32-bit */ |
||||
volatile unsigned magic; /* magic register (R) 32-bit */ |
||||
} yanu_uart_t; |
||||
|
||||
#endif |
||||
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Reference in new issue