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@ -137,8 +137,20 @@ |
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/*
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* IPB Bus clocking configuration. |
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*/ |
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#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ |
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#define CFG_IPBSPEED_133 /* define for 133MHz speed */ |
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#if defined(CFG_IPBSPEED_133) |
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/*
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* PCI Bus clocking configuration |
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* |
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* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if |
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* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't |
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* been tested with a IPB Bus Clock of 66 MHz. |
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*/ |
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#define CFG_PCISPEED_66 /* define for 66MHz speed */ |
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#endif |
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#endif |
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/*
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* I2C configuration |
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*/ |
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@ -263,7 +275,16 @@ |
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#define CFG_BOOTCS_START CFG_FLASH_BASE |
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#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
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#define CFG_BOOTCS_CFG 0x00047801 |
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#ifdef CFG_PCISPEED_66 |
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/*
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* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). |
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*/ |
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#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */ |
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#else |
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#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */ |
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#endif |
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#define CFG_CS0_START CFG_FLASH_BASE |
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#define CFG_CS0_SIZE CFG_FLASH_SIZE |
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