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@ -41,6 +41,13 @@ |
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#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) |
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#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) |
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#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) |
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#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) |
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#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) |
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#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) |
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#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) |
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#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) |
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#define SG_MEMCONF_SPARSEMEM (0x1 << 4) |
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/* Pin Control */ |
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@ -189,6 +196,43 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num) |
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} |
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return ret; |
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} |
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static inline u32 sg_memconf_val_ch2(unsigned long size, int num) |
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{ |
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int size_mb = size / num; |
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u32 ret; |
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switch (size_mb) { |
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case SZ_64M: |
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ret = SG_MEMCONF_CH2_SZ_64M; |
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break; |
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case SZ_128M: |
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ret = SG_MEMCONF_CH2_SZ_128M; |
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break; |
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case SZ_256M: |
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ret = SG_MEMCONF_CH2_SZ_256M; |
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break; |
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case SZ_512M: |
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ret = SG_MEMCONF_CH2_SZ_512M; |
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break; |
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default: |
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BUG(); |
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break; |
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} |
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switch (num) { |
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case 1: |
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ret |= SG_MEMCONF_CH2_NUM_1; |
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break; |
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case 2: |
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ret |= SG_MEMCONF_CH2_NUM_2; |
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break; |
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default: |
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BUG(); |
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break; |
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} |
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return ret; |
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} |
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#endif /* __ASSEMBLY__ */ |
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#endif /* ARCH_SG_REGS_H */ |
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