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@ -86,18 +86,18 @@ |
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/* Micron MT41K256M16HA-125E */ |
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#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 |
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#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB |
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#define MT41K256M16HA125E_EMIF_TIM2 0x26437FDA |
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#define MT41K256M16HA125E_EMIF_TIM3 0x501F83FF |
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2 |
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#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA |
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#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F |
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 |
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#define MT41K256M16HA125E_EMIF_SDREF 0xC30 |
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#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 |
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#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 |
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#define MT41K256M16HA125E_RATIO 0x80 |
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#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 |
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#define MT41K256M16HA125E_RD_DQS 0x3A |
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#define MT41K256M16HA125E_WR_DQS 0x42 |
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#define MT41K256M16HA125E_PHY_WR_DATA 0x7E |
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#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B |
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#define MT41K256M16HA125E_RD_DQS 0x38 |
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#define MT41K256M16HA125E_WR_DQS 0x44 |
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#define MT41K256M16HA125E_PHY_WR_DATA 0x7D |
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#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 |
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#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B |
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/* Micron MT41J512M8RH-125 on EVM v1.5 */ |
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