At present exynos_fimd.c is the controller and exynos_fb.c is the U-Boot LCD interface. With driver model we want these in one file, so join them in preparation. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>master
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/*
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* Copyright (C) 2012 Samsung Electronics |
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* |
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* Author: InKi Dae <inki.dae@samsung.com> |
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* Author: Donghwa Lee <dh09.lee@samsung.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <asm/io.h> |
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#include <lcd.h> |
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#include <div64.h> |
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#include <fdtdec.h> |
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#include <libfdt.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cpu.h> |
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#include "exynos_fb.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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static void exynos_fimd_set_dualrgb(struct vidinfo *pvid, unsigned int enabled) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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if (enabled) { |
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cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | |
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EXYNOS_DUALRGB_VDEN_EN_ENABLE; |
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/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */ |
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cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) | |
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EXYNOS_DUALRGB_MAIN_CNT(0); |
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} |
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writel(cfg, &fimd_ctrl->dualrgb); |
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} |
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static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid, |
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unsigned int enabled) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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if (enabled) |
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cfg = EXYNOS_DP_CLK_ENABLE; |
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writel(cfg, &fimd_ctrl->dp_mie_clkcon); |
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} |
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static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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/* set window control */ |
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cfg = readl((unsigned int)&fimd_ctrl->wincon0 + |
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EXYNOS_WINCON(win_id)); |
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cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | |
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EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE | |
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EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK | |
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EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK); |
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/* DATAPATH is DMA */ |
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cfg |= EXYNOS_WINCON_DATAPATH_DMA; |
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cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; |
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/* dma burst is 16 */ |
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cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; |
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switch (pvid->vl_bpix) { |
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case 4: |
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cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; |
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break; |
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default: |
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cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; |
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break; |
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} |
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writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + |
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EXYNOS_WINCON(win_id)); |
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/* set window position to x=0, y=0*/ |
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cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0); |
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writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a + |
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EXYNOS_VIDOSD(win_id)); |
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cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) | |
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EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) | |
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EXYNOS_VIDOSD_RIGHT_X_E(1) | |
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EXYNOS_VIDOSD_BOTTOM_Y_E(0); |
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writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b + |
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EXYNOS_VIDOSD(win_id)); |
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/* set window size for window0*/ |
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cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row); |
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writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c + |
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EXYNOS_VIDOSD(win_id)); |
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} |
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static void exynos_fimd_set_buffer_address(struct vidinfo *pvid, |
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unsigned int win_id, |
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ulong lcd_base_addr) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned long start_addr, end_addr; |
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start_addr = lcd_base_addr; |
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end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) * |
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pvid->vl_row); |
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writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 + |
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EXYNOS_BUFFER_OFFSET(win_id)); |
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writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 + |
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EXYNOS_BUFFER_OFFSET(win_id)); |
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} |
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static void exynos_fimd_set_clock(struct vidinfo *pvid) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0, div = 0, remainder, remainder_div; |
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unsigned long pixel_clock; |
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unsigned long long src_clock; |
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if (pvid->dual_lcd_enabled) { |
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pixel_clock = pvid->vl_freq * |
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(pvid->vl_hspw + pvid->vl_hfpd + |
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pvid->vl_hbpd + pvid->vl_col / 2) * |
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(pvid->vl_vspw + pvid->vl_vfpd + |
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pvid->vl_vbpd + pvid->vl_row); |
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} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) { |
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pixel_clock = pvid->vl_freq * |
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pvid->vl_width * pvid->vl_height * |
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(pvid->cs_setup + pvid->wr_setup + |
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pvid->wr_act + pvid->wr_hold + 1); |
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} else { |
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pixel_clock = pvid->vl_freq * |
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(pvid->vl_hspw + pvid->vl_hfpd + |
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pvid->vl_hbpd + pvid->vl_col) * |
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(pvid->vl_vspw + pvid->vl_vfpd + |
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pvid->vl_vbpd + pvid->vl_row); |
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} |
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cfg = readl(&fimd_ctrl->vidcon0); |
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cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK | |
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EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK | |
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EXYNOS_VIDCON0_CLKDIR_MASK); |
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cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | |
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EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED); |
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src_clock = (unsigned long long) get_lcd_clk(); |
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/* get quotient and remainder. */ |
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remainder = do_div(src_clock, pixel_clock); |
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div = src_clock; |
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remainder *= 10; |
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remainder_div = remainder / pixel_clock; |
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/* round about one places of decimals. */ |
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if (remainder_div >= 5) |
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div++; |
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/* in case of dual lcd mode. */ |
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if (pvid->dual_lcd_enabled) |
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div--; |
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cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1); |
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writel(cfg, &fimd_ctrl->vidcon0); |
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} |
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void exynos_set_trigger(struct vidinfo *pvid) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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cfg = readl(&fimd_ctrl->trigcon); |
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cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG); |
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writel(cfg, &fimd_ctrl->trigcon); |
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} |
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int exynos_is_i80_frame_done(struct vidinfo *pvid) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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int status; |
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cfg = readl(&fimd_ctrl->trigcon); |
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/* frame done func is valid only when TRIMODE[0] is set to 1. */ |
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status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) == |
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EXYNOS_I80STATUS_TRIG_DONE; |
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return status; |
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} |
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static void exynos_fimd_lcd_on(struct vidinfo *pvid) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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/* display on */ |
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cfg = readl(&fimd_ctrl->vidcon0); |
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cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE); |
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writel(cfg, &fimd_ctrl->vidcon0); |
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} |
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static void exynos_fimd_window_on(struct vidinfo *pvid, unsigned int win_id) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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/* enable window */ |
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cfg = readl((unsigned int)&fimd_ctrl->wincon0 + |
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EXYNOS_WINCON(win_id)); |
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cfg |= EXYNOS_WINCON_ENWIN_ENABLE; |
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writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + |
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EXYNOS_WINCON(win_id)); |
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cfg = readl(&fimd_ctrl->winshmap); |
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cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id); |
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writel(cfg, &fimd_ctrl->winshmap); |
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} |
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void exynos_fimd_lcd_off(struct vidinfo *pvid) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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cfg = readl(&fimd_ctrl->vidcon0); |
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cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); |
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writel(cfg, &fimd_ctrl->vidcon0); |
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} |
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void exynos_fimd_window_off(struct vidinfo *pvid, unsigned int win_id) |
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{ |
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struct exynos_fb *fimd_ctrl = pvid->fimd_ctrl; |
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unsigned int cfg = 0; |
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cfg = readl((unsigned int)&fimd_ctrl->wincon0 + |
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EXYNOS_WINCON(win_id)); |
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cfg &= EXYNOS_WINCON_ENWIN_DISABLE; |
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writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + |
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EXYNOS_WINCON(win_id)); |
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cfg = readl(&fimd_ctrl->winshmap); |
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cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id); |
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writel(cfg, &fimd_ctrl->winshmap); |
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} |
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/*
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* The reset value for FIMD SYSMMU register MMU_CTRL is 3 |
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* on Exynos5420 and newer versions. |
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* This means FIMD SYSMMU is on by default on Exynos5420 |
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* and newer versions. |
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* Since in u-boot we don't use SYSMMU, we should disable |
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* those FIMD SYSMMU. |
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* Note that there are 2 SYSMMU for FIMD: m0 and m1. |
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* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3. |
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* We disable both of them here. |
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*/ |
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void exynos_fimd_disable_sysmmu(void) |
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{ |
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u32 *sysmmufimd; |
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unsigned int node; |
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int node_list[2]; |
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int count; |
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int i; |
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd", |
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COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2); |
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for (i = 0; i < count; i++) { |
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node = node_list[i]; |
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if (node <= 0) { |
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debug("Can't get device node for fimd sysmmu\n"); |
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return; |
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} |
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sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); |
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if (!sysmmufimd) { |
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debug("Can't get base address for sysmmu fimdm0"); |
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return; |
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} |
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writel(0x0, sysmmufimd); |
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} |
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} |
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void exynos_fimd_lcd_init(struct vidinfo *pvid, ulong lcd_base_address) |
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{ |
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struct exynos_fb *fimd_ctrl; |
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unsigned int cfg = 0, rgb_mode; |
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unsigned int offset; |
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unsigned int node; |
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node = fdtdec_next_compatible(gd->fdt_blob, |
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0, COMPAT_SAMSUNG_EXYNOS_FIMD); |
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if (node <= 0) |
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debug("exynos_fb: Can't get device node for fimd\n"); |
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fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, node, |
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"reg"); |
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if (fimd_ctrl == NULL) |
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debug("Can't get the FIMD base address\n"); |
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pvid->fimd_ctrl = fimd_ctrl; |
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if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu")) |
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exynos_fimd_disable_sysmmu(); |
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offset = exynos_fimd_get_base_offset(); |
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rgb_mode = pvid->rgb_mode; |
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if (pvid->interface_mode == FIMD_RGB_INTERFACE) { |
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cfg |= EXYNOS_VIDCON0_VIDOUT_RGB; |
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writel(cfg, &fimd_ctrl->vidcon0); |
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cfg = readl(&fimd_ctrl->vidcon2); |
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cfg &= ~(EXYNOS_VIDCON2_WB_MASK | |
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EXYNOS_VIDCON2_TVFORMATSEL_MASK | |
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EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK); |
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cfg |= EXYNOS_VIDCON2_WB_DISABLE; |
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writel(cfg, &fimd_ctrl->vidcon2); |
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/* set polarity */ |
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cfg = 0; |
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if (!pvid->vl_clkp) |
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cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE; |
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if (!pvid->vl_hsp) |
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cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT; |
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if (!pvid->vl_vsp) |
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cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT; |
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if (!pvid->vl_dp) |
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cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; |
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writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset); |
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/* set timing */ |
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cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1); |
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cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1); |
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cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1); |
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writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset); |
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cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1); |
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cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1); |
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cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1); |
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writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset); |
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/* set lcd size */ |
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cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) | |
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EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) | |
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EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) | |
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EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1); |
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writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset); |
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} |
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/* set display mode */ |
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cfg = readl(&fimd_ctrl->vidcon0); |
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cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK; |
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cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT); |
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writel(cfg, &fimd_ctrl->vidcon0); |
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/* set par */ |
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exynos_fimd_set_par(pvid, pvid->win_id); |
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/* set memory address */ |
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exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address); |
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/* set buffer size */ |
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cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) | |
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EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) | |
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EXYNOS_VIDADDR_OFFSIZE(0) | |
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EXYNOS_VIDADDR_OFFSIZE_E(0); |
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writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 + |
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EXYNOS_BUFFER_SIZE(pvid->win_id)); |
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/* set clock */ |
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exynos_fimd_set_clock(pvid); |
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/* set rgb mode to dual lcd. */ |
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exynos_fimd_set_dualrgb(pvid, pvid->dual_lcd_enabled); |
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/* display on */ |
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exynos_fimd_lcd_on(pvid); |
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/* window on */ |
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exynos_fimd_window_on(pvid, pvid->win_id); |
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exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled); |
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} |
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unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid) |
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{ |
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return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8); |
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} |
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Reference in new issue